Basys 3 Getting started in Microblaze

This guide will provide a step by step walk-through of creating a Microblaze based hardware design using the Vivado IP Integrator for the Basys 3 FPGA board.

At the end of this tutorial you will have:

• Created a Microblaze based hardware ( HW ) design in Xilinx Vivado

• Created a .C Project in Xilinx Vivado SDK ( Software Development Kit) to display Hello World using the hardware design shown in the previous step

• Displayed the final output on both the SDK console and Tera Term

• Digilent Basys 3 FPGA Board and Micro USB Cable for UART communication and JTAG programming

• Xilinx Vivado 2016.X with the SDK package.

• Board Support Files
  • These files will describe GPIO interfaces on your board and make it easier to select your FPGA board and add GPIO IP blocks
  • Follow this Wiki guide (Vivado Board Files for Digilent 7-Series FPGA Boards ) on how to install Board Support Files for Vivado

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Microblaze is a soft IP core from Xilinx that will implement a microprocessor entirely within the Xilinx FPGA general purpose memory and logic fabric. For this tutorial, we are going to add a Microblaze IP block using the Vivado IP Integrator tool.

In addition to the Microblaze IP block, a UART ( universal asynchronous receiver/transmitter ) IP block will be added to communicate between the host PC and the soft processor core running on the Basys 3.

I. Vivado

• Open Vivado and select Basys 3 board
• Create an new Vivado Project
• Create empty block design workspace inside the new project
• Add required IP blocks using the IP integrator tool and build Hardware Design
• Validate and save block design
• Create HDL system wrapper
• Run design Synthesis and Implementation
• Generate Bit File
• Export Hardware Design including the generated bit stream file to SDK tool
• Launch SDK

Now the Hardware design is exported to the SDK tool. The Vivado to SDK hand-off is done internally through Vivado. We will use SDK to create a Software application that will use the customized board interface data and FPGA hardware configuration by importing the hardware design information from Vivado.

II. SDK

• Create new application project and select default Hello World template
• Program FPGA
• Run configuration by selecting the correct UART COM Port and Baud Rate

When you first run Vivado this will be the main start window where you can create a new project or open a recent one.

1.1) Click on Create New Project. Choose the Project Name and Location such that there are no blank spaces. This is an important naming convention to follow for project names, file names and location paths. Underscore is a good substitute for empty spaces. It is good practice to have a dedicated folder for Vivado Projects, preferably with the smallest possible path length. Example: C:/Vivado_Projects. Name your Project and select the Project location and click Next.

1.2) Choose Project Type as RTL Project. Leave the Do not specify sources box unchecked and click Next.

1.3) If you have followed the Board Support File Wiki guide then click next until you can select Boards. From the filter options make required selections for Vendor, Display Name and Board Revision. Basys 3 should be displayed in the selection list. A mismatch in selecting the correct board name will cause errors. Choose Basys 3 and click next.

1.4) A summary of the new project design sources and target device is displayed. Click Finish.

2.1) This is the main project window where you can create a IP based block design or add RTL based design sources. The flow navigator panel on the left provides multiple options on how to create a hardware design, perform simulation, run synthesis and implementation and generate a bit file. You can also program the board directly from Vivado with the generated bit file for an RTL project using the Hardware Manager. For our design, we will use the IP Integrator to create a new block design.

2.2) On the left you should see the Flow Navigator. Select Create Block Design under the IP Integrator. Give a name to your design without any empty spaces.

2.3) An empty design workspace is created where you can add IP blocks. Add an IP core by clicking on the Add IP icon. This should open a catalog of pre-built IP blocks from Xilinx IP repository.

3.1) Click the Board tab

This list contains all of the components defined in the board file you installed before. These are already configured to work with several Vivado IPs.

3.2) Click and drag the System Clock component onto the empty block design. Vivado will automatically connect this system clock to a new Clocking Wizard block.

3.3) Double click the Clocking Wizard block to customize it. Click on the Output Clocks tab. Make sure clk_out1 is “100.000” and the Reset Type is Active High

4.1) Add an IP core by clicking on the Add IP icon. Search for “Microblaze” and double click on it to add the IP block to your design. This is the Xilinx Microblaze IP block. When a new IP block is added the user can customize the block properties by either clicking on the Run Block Automation message prompt or by double clicking on the block itself.

4.2) Select Run Block Automation and a customization assistant window will open with default settings.

4.3) Change default settings in the block options as shown below and click OK. This will customize the block with our new user settings.

Local Memory: 128KB
Local Memory ECC: None
Cache Configuration: None
Debug Module: Debug only
Peripheral AXI Port: Enabled
Interrupt Controller: unchecked
Clock Connection: /clk_wiz0/clk_out1(100 MHZ)



4.4) Running the block automation will auto-generate a set of additional IP blocks which will be added to our hardware design automatically based on the options selected in the previous step. Do not click on Run Connection Automation yet.

5.1) Go into the Boards tab again and find the USB UART component. Click and drag this onto the block design to add the Uartlite block to your design.

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5.2) Click Run Connection Automation in the green banner. Check the All Automation box and then click OK.

5.3) Click Run Connection Automation again in the green banner. Check the All Automation box and then click OK.

5.4) Select Validate Design. This will check for design and connection errors.


5.5) Click the Regenerate Layout button to rearrange your block design. The block design should look like



5.6) Select Validate Design. This will check for design and connection errors.

6.1) After the design validation step we will proceed with creating a HDL System Wrapper. Click on the Sources tab and find your block design.



6.2) Right click on your block design and click Create HDL Wrapper. Make sure Let Vivado manage wrapper and auto-update is selected and click OK.



This will create a top module in Verilog and will allow you to generate a bitstream.

7.1) Click Generate bitstream

8.1) On the main toolbar, click File and select Export→Export Hardware. Check the box to Include Bitstream and click OK. This will export the hardware design with system wrapper for the Software Development Tool - Vivado SDK.



A new file directory will be created under Hello_World.SDK similar to the Vivado hardware design project name. Two other files, .sysdef and .hdf are also created. This step essentially creates a new SDK Workspace.

8.2) On the main toolbar, click File and then Launch SDK. Leave both of the dropdown menus as their default Local to Project and click OK. This will open Xilinx SDK and import your hardware.

9.1) Click the New dropdown arrow and select Xilinx→Application Project.



Give your project a name that has no empty spaces and click Next.

9.2) Select Hello World from the list of templates and click Finish.

You will see two new folders in the Project Explorer panel.

• Hello_world which contains all the binaries, .C and .H (Header) files
• Hello_world_bsp which is the board support folder

Hello_world is our main working source folder. This also contains an important file shown here which is the “lscript.ld”. This is a Xilinx auto generated linker script file. Double click on this file to open.

9.3) Back in the Project Explorer, double click and open helloworld.c under the src folder.

This is the main .C file which will print “Hello World” in the console when executed.

10.1) Make sure that the Basys 3 is turned on and connected to the host PC via the USB-JTAG port - this port will serve dual purpose as the USB-UART connection to the Microblaze.

On the top toolbar, click the Program FPGA button.

10.2) Click Program to program your FPGA with your hardware design.

11.1) Open up a Serial Terminal application(Terra Term). Connect to the Basys 3 UART port with a baud rate of 9600. This baud rate can be altered in your block design by double clicking the Uartlite block.



11.2) With Tera Term serial port settings

12.1) Back in SDK, select your Hello_world project and click the Run As… button. Select Launch on Hardware (System Debugger) and click OK.

12.2) Your program will run and you should see “Hello World” pop up inside of your Serial Terminal. Hooray!