Pmod IP Design Requirements

The tables below present information on what Pmods and boards are supported by Pmod IPs, as well as additional design requirements for using each Pmod IP.

Table of Contents

Table 1: Platforms Supported

Platform Processor Type
Arty A7 Microblaze
Arty S7 Microblaze
Arty Z7 Zynq
Basys3 Microblaze
Cmod A7 Microblaze
Cmod S7 Microblaze
Cora Z7 Zynq
Genesys2 Microblaze
Nexys A7 Microblaze
Nexys Video Microblaze
USB104 A7 Microblaze
Zybo Z7 Zynq

Table 2: Pmods Supported

Pmod Pmod IP Core Interface Type Additional Notes
8LD PmodGPIO_v1_0 GPIO -
ACL PmodACL_v1_0 SPI -
ACL2 PmodACL2_v1_0 SPI -
AD1 PmodAD1_v1_0 SPI -
AD2 PmodAD2_v1_0 IIC -
AD5 PmodAD5_v1_0 SPI -
ALS PmodALS_v1_0 SPI -
AMP2 PmodAMP2_v1_0 GPIO -
AQS PmodAQS_v1_0 IIC -
BB PmodGPIO_v1_0 GPIO -
BLE PmodBLE_v1_0 UART -
BT2 PmodBT2_v1_0 UART -
BTN PmodGPIO_v1_0 GPIO -
CAN PmodCAN_v1_0 SPI -
CLS PmodCLS_v1_0 SPI -
CMPS2 PmodCMPS2_v1_0 IIC Software example requires math.h - see Xilinx Answer Record 52971
COLOR PmodCOLOR_v1_0 IIC -
DA1 PmodDA1_v1_0 SPI -
DHB1 PmodDHB1_v1_0 PWM/GPIO -
DPG1 PmodDPG1_v1_0 SPI -
ENC PmodENC_v1_0 GPIO -
ESP32 PmodESP32_v1_0 UART -
GPS PmodGPS_v1_1 UART -
GYRO PmodGYRO_v1_0 SPI -
HYGRO PmodHYGRO_v1_0 IIC -
JSTK PmodJSTK_v1_0 SPI -
JSTK2 PmodJSTK2_v1_0 SPI -
KYPD PmodKYPD_v1_0 GPIO -
LED PmodGPIO_v1_0 GPIO -
MAXSONAR PmodMAXSONAR_v1_0 GPIO -
MicroSD PmodSD_v1_0 SPI -
MTDS PmodMTDS_v1_0 SPI -
NAV PmodNAV_v1_0 SPI/GPIO -
OLED PmodOLED_v1_0 SPI/GPIO -
OLEDrgb pmodOLEDrgb_v1_0 SPI/GPIO -
PIR PmodPIR_v1_0 GPIO -
R2R PmodR2R_v1_0 GPIO -
RTCC PmodRTCC_v1_0 IIC -
SD PmodSD_v1_0 SPI -
SF3 PmodSF3_v1_0 SPI -
SSR PmodGPIO_v1_0 GPIO -
SWT PmodGPIO_v1_0 GPIO -
TC1 PmodTC1_v1_0 SPI -
TMP3 PmodTMP3_v1_0 IIC -
WIFI PmodWIFI_v1_0 SPI 385 KB Minimum Program Memory

Table 3: Clocking Requirements for Pmod IPs

Note: Pmod IPs not present in this table do not have any specific clocking recommendations.

Pmod IP Core AXI Clock Requirement (MHz) Reference Clock Name Maximum Reference Clock Frequency (MHz)
PmodACL_v1_0 - ext_spi_clk 80
PmodACL2_v1_0 - ext_spi_clk 50
PmodAD1_v1_0 100 MHz AXI Clock Required - -
PmodAD5_v1_0 - ext_spi_clk 50
PmodALS_v1_0 - ext_spi_clk 50
PmodCAN_v1_0 - ext_spi_clk 100
PmodCLS_v1_0 - ext_spi_clk 50
PmodDA1_v1_0 - ext_spi_clk 50
PmodDPG1_v1_0 - ext_spi_clk 50
PmodGYRO_v1_0 - ext_spi_clk 50
PmodJSTK_v1_0 - ext_spi_clk 16
PmodJSTK2_v1_0 - ext_spi_clk 16
PmodMTDS_v1_0 56 MHz Maximum - -
PmodNAV_v1_0 - ext_spi_clk 50
pmodOLEDrgb_v1_0 - ext_spi_clk 50
PmodSD_v1_0 32 MHz Maximum (Recommended) - -
PmodSF3_v1_0 - ext_spi_clk 50
PmodTC1_v1_0 - ext_spi_clk 50
PmodWIFI_v1_0 200 MHz Maximum (For a 25 MHz SPI Clock) - -

Table 4: Interrupt Requirements for Pmod IPs

Note: Pmod IP Cores not present in this table do not have interrupt pins.

Pmod IP Core Interrupt pin name/s Interrupt Required for Software Example
PmodAMP2_v1_0 timer_interrupt Yes
PmodCAN_v1_0 SPI_interrupt, GPIO_interrupt No
PmodGPS_v1_1 gps_uart_interrupt Yes
PmodSF3_v1_0 QSPI_INTERRUPT Yes
PmodWIFI_v1_0 WF_INTERRUPT Yes

Table 5: Programming Language for Pmod Software Examples

Note: Unless otherwise listed, the software example for this Pmod was written in C.

Pmod IP Core Programming Language
PmodMTDS_v1_0 C++
PmodSD_v1_0 C++
PmodWIFI_v1_0 C++