Verilog HDL Background and History

Introduction to Hardware Description Language

Hardware Description Language (HDL) was introduced as a means to provide a detailed design specification of a digital circuit, with little thought given to how a circuit might be implemented based on that specification (the assumption was the requirements in the source file would be captured as a schematic by a skilled engineer). At the time, the creation of a design specification, although involved, was almost trivial in comparison to the amount of work required to translate the specification to a schematic-based structural description needed to fabricate a device. Over several years, it became clear that a computer program could be written to automatically translate a HDL behavioral specification to a structural circuit, and a new class of computer programs called synthesizers began appearing. A synthesizer produces a low-level, structural description of a circuit based on its HDL description. This automated behavioral-to-structural translation of a circuit definition greatly reduced the amount of human effort required to produce a circuit.

The use of HDLs and synthesizers has revolutionized the way in which digital engineers work, and it is important to keep in mind how rapidly this change has come about. In 1990, very few new designs were started using HDLs (the vast majority were schematic based). By the mid 1990s, roughly half of all new designs were using HDLs, and today, all but the most trivial designs use HDL methods. Such rapid change demonstrates the recognition of engineers to the overwhelming advantages of using HDLs.

But such rapid change also means that tools, methods, and technologies are still evolving, and that CAD tools are continuing to be developed and improved upon. Digital design CAD tools can be placed in two major categories. the “front-end” tools that allow a design to be captured and simulated, and “back-end” tools that synthesize a design, map it to a particular technology, and analyze its performance (thus, front-end tools work mostly with virtual circuits, and back-end tools work mostly with physical circuits). Several companies produce CAD tools, with some focusing on front-end tools, some on back-end tools, and some on both. Two major HDLs have emerged, one developed by and for private industry (called Verilog®), and the other fueled by the government and specified by IEEE (VHDL). Both are similar in appearance and application, and both have their relative advantages. We will use Verilog in this course because it is used more commonly in the industry today. It should be noted that after learning one of the two languages, the other can be adopted quickly.

HDLs have allowed design engineers to increase their productivity manyfold in just a few years. It is fair to say that a well-equipped engineer today is as productive as a small team of engineers just a few years ago. Furthermore, hardware specification is now within the reach of a wider range of engineers; no longer is it the domain of only a few with highly specialized training and experience. In order to support this increased level of productivity, engineers must master a new set of design skills: they must be able to craft behavioral circuit definitions that provably meet design requirements; they must understand synthesis and other CAD tool processes so that results can be critically examined and interpreted; and they must be able to model external interfaces to the design so that it can be rigorously tested and verified. The extra degree of abstraction that HDL allows brings many new sources of potential errors, and designers must be able to recognize and address such errors when they occur.

Verilog HDL: A Brief History

Verilog HDL was invented by Phil Moorby and Prabhu Goel around 1984. It served as a proprietary hardware modeling language owned by Gateway Design Automation Inc. At that time, the language was not standardized. It modified itself in almost all the revisions that came out between 1984 to 1990.

In 1990, Gateway Design Automation Inc was acquired by Cadence Design System, which is now one of the biggest suppliers of electronic design technologies and engineering services in the electronic design automation (EDA) industry. Cadence recognized the value of Verilog, and realized that if Verilog remained as a closed language, the pressure of standardization would eventually drive people to shift to VHDL. So in 1991 the Open Verilog International (OVI) (now known as Accellera) was organized by Candence and the documentation of Verilog was transferred to public domain under the name of OVI. It was later submitted to IEEE and became IEEE standard 1364-1995, commonly referred as Verilog-95.

In 2001, extensions to Verilog-95 were submitted back to IEEE and became IEEE standard 1364-2001, known as Verilog-2001. The extensions covered some deficiencies that users had found in the Verilog-95. One of the most significant upgrades was that signed variables (in 2.s complement) became supported. Verilog-2001 is now the dominant edition of Verilog supported by most design tools.

In 2005, Verilog-2005 (IEEE Standard 1364-2005) was published with minor corrections and modifications. Also in 2005 System Verilog, a superset of Verilog-2005, with many new features and capabilities to aid design verification, was published. As of 2009, SystemVerilog and Verilog language standards were merged into SystemVerilog 2009 (IEEE Standard 1800-2009), which is one of the most popular languages for IC design and verification today. Xilinx® Vivado Design Suite, released in 2013, can support SystemVerilog for FPGA design and verification.