FMC-HDMI Reference Manual

Revised September 3, 2014

This manual applies to REV D of the board.

The FPGA Mezzanine Card High-Definition Multimedia Interface (FMC-HDMI) peripheral board enables developers to add HDMI input ports to field-programmable gate array (FPGA) based systems. The FMC-HDMI provides a development platform for customers to utilize high-definition image capturing for use with image processing applications.

Features include:

• (2x) HDMI Type A Receptacles
• HDMI Receiver (ADV7611)
• HDMI Buffer (AD8195)
• On-board EDID EEPROM
• Male FMC LPC connector for digital signals
• Compatible with a wide range of VADJ voltages (1.8V – 3.3V)

The FMC-HDMI card contains two HDMI input ports. The first port, HDMI1, contains an ADI ADV7611 Receiver and outputs a decoded, level translated digital video signal to the FMC connector. The second port, HDMI2, contains an ADI AD8195 Buffer and outputs an HDMI-encoded signal to the FMC connector, leaving the system board to decode the signal (either in the FPGA or an external receiver).

The appropriateness of the HDMI port depends entirely on the application. For instance, although HDMI2 does not decode the signal, it outputs to a smaller number of pins (14 instead of 36), which is useful in designs with limited input availability. Since the decoding must be done on the connected system board, the circuitry must support HDMI-type signaling that is TMDS. For example, Xilinx® FPGA families support the TMDS_33 input standard in 3.3V-powered I/O banks.

An Analog Devices ADV7611 Receiver decodes the signal on HDMI1. This low power, 165 MHz receiver supports formats up to UXGA 60Hz at 8 bit at 161 MHz. It has been tested at WUXGA (1080p) 60Hz at 148.5 MHz. The receiver provides an audio output port for audio extracted from the HDMI signal in the following formats: I2S, S/PDIF, and Direct Stream Transfer (DST). It also features an advanced mute controller.

The ADV7611 Receiver contains several other features, such as a CEC 1.4-compatible controller for consumer device remote control and discovery and EDID (Extended Display Identification Data) RAM.

Note: For more information on the ADV7611, see ADI datasheets and User Guide available online at: http://www.analog.com/ADV7611

Below are the pin-outs from the ADV7611 Receiver and other HDMI1 port signals to the FMC connector:

Table 1. HDMI1-FMC pin mapping

The ADV7611 is configured and controlled via an I2C interface, which is accessible through the HDMI1SDA and HDMI1SCL pins on the FMC connector. The ADV7611 User Guide specifically describes the different registers and commands necessary to control the Receiver.

There are level translators present on all audio and video signals, which can level shift to 1.8V, 2.5V, and 3.3V. The desired level is set by the VADJ voltage level.

The AD8195 is an HDMI buffer with equalized TMDS inputs and optionally pre-emphasized TMDS outputs. The AD8195 includes bidirectional buffering for the DDC bus and bidirectional buffering with integrated pull-up resistors for the CEC bus. The DDC and CEC buffers are powered independently of the TMDS buffers so that DDC/CEC functionality can be maintained when the system is powered off.

An on-board pre-programmed EEPROM is connected to the DDC (Display Data Channel) bus of the HDMI2 port. The following EDID (Extended Display Identification Data) is programmed in the factory:

Table 2. EEPROM pre-programmed content.

The EEPROM can be freely re-written through the J4 header holes and 6-pin Pmod cable. During EEPROM programming, power to the EEPROM is provided by pin 6 of J4, so make sure there is no HDMI cable plugged in at the same time.

Below are the pin-outs from the AD8195 Buffer and other HDMI2 port signals to the FMC connector:

Table 3. HDMI2-FMC pin mapping.

WARNING: VADJ must be 3.3V to properly use the buffer on HDMI2. The TX_EN pin is held low by default, so the buffer is disabled on power-up. With the buffer disabled, VADJ can be in the range of (1.8V-3.3V).

Note: For more information on the AD8195, see ADI datasheets available online at http://www.analog.com/AD8195

The FMC-HDMI uses a Samtec ASP-134604-01 low pin-count male connector as the main connector for digital signals. The board fully conforms to the VITA 57.1 specs. The connector supports the full range of 1.8V-3.3V bank supply voltages (VADJ).

I²C serves as the IPMI EEPROM, providing hardware definition information. For more information, consult the VITA 57.1 specs.

Issue #1: The on-board FMC EEPROM contents do not conform to the VITA 57.1 FPGA Mezzanine Card (FMC) Standard and the IPMI Platform Management FRU Information Storage Specifications.

Affected systems: Management software that read and rely on FRU data for some functionality.

Impact: minor.

Solution: Use the published FMC-HDMI-frufix project, created in Vivado 2016.4 and targeting the Digilent Zedboard, to reprogram the EEPROM with the correct image. The project can also be adapted to any other Xilinx FPGA board available.