Signal Name | Total Pterms | Total Inputs | Function Block | Macrocell | Slew Rate | Bank | Pin Number | Pin Type | Pin Use | Reg Use | I/O Std | I/O Style | Reg Init State |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Inst_Timer_Block/S_HUNS<2> | 2 | 6 | FB2 | MC1 | 2 | 2 | I/O/GTS2 | (b) | TFF | RESET | |||
Inst_Timer_Block/T0/TC_ONES | 4 | 8 | FB2 | MC3 | 2 | 3 | I/O/GTS3 | (b) | DFF | RESET | |||
Inst_Timer_Block/S_THOU<2> | 2 | 7 | FB2 | MC4 | 2 | 4 | I/O | (b) | TFF | RESET | |||
Inst_Timer_Block/T0/TC_TENS | 5 | 9 | FB2 | MC5 | 2 | 5 | I/O/GTS0 | (b) | DFF | RESET | |||
Inst_Timer_Block/T0/TC_HUNS | 6 | 10 | FB2 | MC12 | 2 | 6 | I/O/GTS1 | (b) | DFF | RESET | |||
Inst_Timer_Block/S_THOU<1> | 4 | 9 | FB2 | MC13 | 2 | 7 | I/O | (b) | TFF | RESET | |||
Inst_Timer_Block/S_THOU<3> | 3 | 9 | FB2 | MC14 | 2 | 9 | I/O | (b) | TFF | RESET | |||
Inst_Timer_Block/S_HUNS<1> | 4 | 8 | FB2 | MC15 | 2 | 10 | I/O | (b) | TFF | RESET | |||
Inst_Timer_Block/S_ONES<2> | 2 | 4 | FB4 | MC12 | 2 | 17 | I/O | (b) | TFF | RESET | |||
Inst_Timer_Block/S_TENS<2> | 2 | 5 | FB4 | MC14 | 2 | 18 | I/O | (b) | TFF | RESET | |||
CAT<1> | 12 | 20 | FB16 | MC16 | FAST | 1 | 53 | I/O | O | LVCMOS18 | |||
CAT<5> | 16 | 18 | FB16 | MC15 | FAST | 1 | 54 | I/O | O | LVCMOS18 | |||
CAT<0> | 14 | 20 | FB16 | MC13 | FAST | 1 | 56 | I/O | O | LVCMOS18 | |||
CAT<4> | 10 | 20 | FB16 | MC12 | FAST | 1 | 57 | I/O | O | LVCMOS18 | |||
CAT<3> | 14 | 20 | FB16 | MC11 | FAST | 1 | 58 | I/O | O | LVCMOS18 | |||
CAT<7> | 1 | 2 | FB16 | MC6 | FAST | 1 | 59 | I/O | O | LVCMOS18 | |||
CAT<2> | 1 | 1 | FB16 | MC5 | FAST | 1 | 60 | I/O | O | LVCMOS18 | |||
CAT<6> | 12 | 18 | FB14 | MC16 | FAST | 1 | 61 | I/O | O | LVCMOS18 | |||
LD<3> | 7 | 15 | FB14 | MC14 | FAST | 1 | 64 | I/O | O | DFF | LVCMOS18 | RESET | |
LD<2> | 1 | 2 | FB14 | MC13 | FAST | 1 | 66 | I/O | O | LVCMOS18 | |||
LD<1> | 1 | 2 | FB14 | MC6 | FAST | 1 | 68 | I/O | O | LVCMOS18 | |||
LD<0> | 1 | 2 | FB14 | MC4 | FAST | 1 | 69 | I/O | O | LVCMOS18 | |||
Inst_Timer_Block/S_ONES<0> | 1 | 1 | FB12 | MC15 | 2 | 94 | I/O | IR | TFF | KPR | |||
ANO<0> | 1 | 2 | FB11 | MC13 | FAST | 2 | 126 | I/O | O | LVCMOS18 | |||
ANO<1> | 1 | 2 | FB11 | MC14 | FAST | 2 | 128 | I/O | O | LVCMOS18 | |||
ANO<2> | 1 | 2 | FB11 | MC15 | FAST | 2 | 129 | I/O | O | LVCMOS18 | |||
ANO<3> | 1 | 2 | FB11 | MC16 | FAST | 2 | 130 | I/O | O | LVCMOS18 | |||
Inst_clk_div/disp_count<5> | 1 | 5 | FB3 | MC16 | 2 | 131 | I/O | (b) | TFF | RESET | |||
Inst_clk_div/disp_count<6> | 1 | 6 | FB3 | MC14 | 2 | 132 | I/O | (b) | TFF | RESET | |||
Inst_clk_div/disp_count<7> | 1 | 7 | FB3 | MC5 | 2 | 133 | I/O | (b) | TFF | RESET | |||
Inst_clk_div/disp_count<8> | 1 | 8 | FB3 | MC3 | 2 | 134 | I/O | (b) | TFF | RESET | |||
Inst_clk_div/disp_count<9> | 1 | 9 | FB3 | MC2 | 2 | 135 | I/O | (b) | TFF | RESET | |||
Inst_clk_div/disp_count<10> | 1 | 10 | FB3 | MC1 | 2 | 136 | I/O | (b) | TFF | RESET | |||
Inst_clk_div/base_count<10> | 2 | 11 | FB1 | MC14 | 2 | 137 | I/O | (b) | TFF | RESET | |||
Inst_clk_div/base_count<12> | 2 | 13 | FB1 | MC13 | 2 | 138 | I/O | (b) | TFF | RESET | |||
Inst_clk_div/base_count<13> | 2 | 14 | FB1 | MC12 | 2 | 139 | I/O | (b) | TFF | RESET | |||
Inst_clk_div/base_count<18> | 2 | 19 | FB1 | MC6 | 2 | 140 | I/O | (b) | TFF | RESET | |||
Inst_clk_div/base_count<19> | 2 | 20 | FB1 | MC4 | 2 | 142 | I/O | (b) | TFF | RESET | |||
Inst_clk_div/base_count<17> | 1 | 17 | FB1 | MC3 | 2 | 143 | I/O/GSR | GSR/I | TFF | KPR | RESET | ||
Inst_clk_div/base_count<8> | 1 | 9 | FB1 | MC1 | (b) | (b) | RESET | ||||||
Inst_clk_div/base_count<7> | 1 | 7 | FB1 | MC2 | (b) | (b) | RESET | ||||||
Inst_clk_div/base_count<6> | 1 | 6 | FB1 | MC5 | (b) | (b) | RESET | ||||||
Inst_clk_div/base_count<5> | 1 | 5 | FB1 | MC7 | (b) | (b) | RESET | ||||||
Inst_clk_div/base_count<4> | 1 | 4 | FB1 | MC8 | (b) | (b) | RESET | ||||||
Inst_clk_div/base_count<3> | 1 | 3 | FB1 | MC9 | (b) | (b) | RESET | ||||||
Inst_clk_div/base_count<2> | 1 | 2 | FB1 | MC10 | (b) | (b) | RESET | ||||||
Inst_clk_div/base_count<1> | 1 | 1 | FB1 | MC11 | (b) | (b) | RESET | ||||||
Inst_clk_div/disp_count<0> | 0 | 0 | FB1 | MC15 | (b) | (b) | RESET | ||||||
Inst_clk_div/base_count<0> | 0 | 0 | FB1 | MC16 | (b) | (b) | RESET | ||||||
Inst_Timer_Block/S_HUNS<3> | 3 | 8 | FB2 | MC2 | (b) | (b) | RESET | ||||||
Inst_Timer_Block/S_TENS<3> | 3 | 7 | FB2 | MC6 | (b) | (b) | RESET | ||||||
Inst_Timer_Block/S_TENS<1> | 3 | 7 | FB2 | MC7 | (b) | (b) | RESET | ||||||
Inst_Timer_Block/S_ONES<3> | 3 | 6 | FB2 | MC8 | (b) | (b) | RESET | ||||||
Inst_Timer_Block/S_ONES<1> | 3 | 6 | FB2 | MC9 | (b) | (b) | RESET | ||||||
N_PZ_467 | 2 | 10 | FB2 | MC10 | (b) | (b) | |||||||
N_PZ_466 | 2 | 10 | FB2 | MC11 | (b) | (b) | |||||||
CAT<2>_BUFR | 12 | 18 | FB2 | MC16 | (b) | (b) | |||||||
Inst_clk_div/disp_count<4> | 1 | 4 | FB3 | MC4 | (b) | (b) | RESET | ||||||
Inst_clk_div/disp_count<3> | 1 | 3 | FB3 | MC6 | (b) | (b) | RESET | ||||||
Inst_clk_div/disp_count<2> | 1 | 2 | FB3 | MC7 | (b) | (b) | RESET | ||||||
Inst_clk_div/disp_count<1> | 1 | 1 | FB3 | MC8 | (b) | (b) | RESET | ||||||
N_PZ_446 | 1 | 12 | FB3 | MC9 | (b) | (b) | |||||||
Inst_clk_div/base_count<9> | 1 | 9 | FB3 | MC10 | (b) | (b) | RESET | ||||||
Inst_clk_div/base_count<11> | 1 | 11 | FB3 | MC11 | (b) | (b) | RESET | ||||||
Inst_clk_div/base_count<14> | 1 | 14 | FB3 | MC12 | (b) | (b) | RESET | ||||||
Inst_clk_div/base_count<15> | 1 | 15 | FB3 | MC13 | (b) | (b) | RESET | ||||||
Inst_clk_div/base_count<16> | 1 | 16 | FB3 | MC15 | (b) | (b) | RESET | ||||||
Inst_Timer_Block/S_THOU<0> | 2 | 5 | FB4 | MC7 | (b) | (b) | RESET | ||||||
Inst_Timer_Block/S_HUNS<0> | 2 | 4 | FB4 | MC8 | (b) | (b) | RESET | ||||||
Inst_Timer_Block/S_TENS<0> | 2 | 3 | FB4 | MC9 | (b) | (b) | RESET | ||||||
Inst_Timer_Block/S_2BIT<1> | 2 | 2 | FB4 | MC10 | (b) | (b) | RESET | ||||||
Inst_Timer_Block/S_2BIT<0> | 1 | 1 | FB4 | MC11 | (b) | (b) | RESET | ||||||
Inst_clk_div/disp_count<11> | 1 | 11 | FB4 | MC13 | (b) | (b) | RESET | ||||||
Inst_clk_div/disp_count<12> | 1 | 12 | FB4 | MC15 | (b) | (b) | RESET | ||||||
s_disp | 1 | 13 | FB4 | MC16 | (b) | (b) | RESET |