Device Utilization Summary | [-] |
Slice Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Registers |
64 |
126,800 |
1% |
|
Number used as Flip Flops |
63 |
|
|
|
Number used as Latches |
0 |
|
|
|
Number used as Latch-thrus |
0 |
|
|
|
Number used as AND/OR logics |
1 |
|
|
|
Number of Slice LUTs |
2,068 |
63,400 |
3% |
|
Number used as logic |
2,066 |
63,400 |
3% |
|
Number using O6 output only |
1,017 |
|
|
|
Number using O5 output only |
50 |
|
|
|
Number using O5 and O6 |
999 |
|
|
|
Number used as ROM |
0 |
|
|
|
Number used as Memory |
0 |
19,000 |
0% |
|
Number used exclusively as route-thrus |
2 |
|
|
|
Number with same-slice register load |
0 |
|
|
|
Number with same-slice carry load |
2 |
|
|
|
Number with other load |
0 |
|
|
|
Number of occupied Slices |
666 |
15,850 |
4% |
|
Number of LUT Flip Flop pairs used |
2,068 |
|
|
|
Number with an unused Flip Flop |
2,005 |
2,068 |
96% |
|
Number with an unused LUT |
0 |
2,068 |
0% |
|
Number of fully used LUT-FF pairs |
63 |
2,068 |
3% |
|
Number of unique control sets |
4 |
|
|
|
Number of slice register sites lost to control set restrictions |
17 |
126,800 |
1% |
|
Number of bonded IOBs |
35 |
210 |
16% |
|
Number of LOCed IOBs |
35 |
35 |
100% |
|
IOB Flip Flops |
17 |
|
|
|
Number of bonded IPADs |
8 |
|
|
|
Number of LOCed IPADs |
8 |
8 |
100% |
|
Number of RAMB36E1/FIFO36E1s |
0 |
135 |
0% |
|
Number of RAMB18E1/FIFO18E1s |
0 |
270 |
0% |
|
Number of BUFG/BUFGCTRLs |
1 |
32 |
3% |
|
Number used as BUFGs |
1 |
|
|
|
Number used as BUFGCTRLs |
0 |
|
|
|
Number of IDELAYE2/IDELAYE2_FINEDELAYs |
0 |
300 |
0% |
|
Number of ILOGICE2/ILOGICE3/ISERDESE2s |
2 |
300 |
1% |
|
Number used as ILOGICE2s |
2 |
|
|
|
Number used as ILOGICE3s |
0 |
|
|
|
Number used as ISERDESE2s |
0 |
|
|
|
Number of ODELAYE2/ODELAYE2_FINEDELAYs |
0 |
|
|
|
Number of OLOGICE2/OLOGICE3/OSERDESE2s |
15 |
300 |
5% |
|
Number used as OLOGICE2s |
15 |
|
|
|
Number used as OLOGICE3s |
0 |
|
|
|
Number used as OSERDESE2s |
0 |
|
|
|
Number of PHASER_IN/PHASER_IN_PHYs |
0 |
24 |
0% |
|
Number of PHASER_OUT/PHASER_OUT_PHYs |
0 |
24 |
0% |
|
Number of BSCANs |
0 |
4 |
0% |
|
Number of BUFHCEs |
0 |
96 |
0% |
|
Number of BUFRs |
0 |
24 |
0% |
|
Number of CAPTUREs |
0 |
1 |
0% |
|
Number of DNA_PORTs |
0 |
1 |
0% |
|
Number of DSP48E1s |
1 |
240 |
1% |
|
Number of EFUSE_USRs |
0 |
1 |
0% |
|
Number of FRAME_ECCs |
0 |
1 |
0% |
|
Number of IBUFDS_GTE2s |
0 |
4 |
0% |
|
Number of ICAPs |
0 |
2 |
0% |
|
Number of IDELAYCTRLs |
0 |
6 |
0% |
|
Number of IN_FIFOs |
0 |
24 |
0% |
|
Number of MMCME2_ADVs |
0 |
6 |
0% |
|
Number of OUT_FIFOs |
0 |
24 |
0% |
|
Number of PCIE_2_1s |
0 |
1 |
0% |
|
Number of PHASER_REFs |
0 |
6 |
0% |
|
Number of PHY_CONTROLs |
0 |
6 |
0% |
|
Number of PLLE2_ADVs |
0 |
6 |
0% |
|
Number of STARTUPs |
0 |
1 |
0% |
|
Number of XADCs |
1 |
1 |
100% |
|
Average Fanout of Non-Clock Nets |
3.73 |
|
|
|