Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
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software_version_and_target_device
date_generatedSun Mar 01 13:24:09 2015 product_versionVivado v2014.4 (64-bit)
build_version1071353 os_platformWIN64
registration_id210658864_0_0_152 tool_flowVivado
betaFALSE route_designTRUE
target_familyartix7 target_devicexc7a100t
target_packagecsg324 target_speed-1
random_id7babad8de19a50189065ad224660438a project_id0001acc516e64c8cbb4cef0e38965b07
project_iteration0

user_environment
os_nameMicrosoft Windows 7 , 64-bit os_releaseService Pack 1 (build 7601)
cpu_nameIntel(R) Core(TM) i7-4710MQ CPU @ 2.50GHz cpu_speed2494 MHz
total_processors1 system_ram8.000 GB

vivado_usage
project_data
srcsetcount=9 constraintsetcount=1 designmode=RTL prproject=false
reconfigpartitioncount=0 reconfigmodulecount=0 hdproject=false partitioncount=0
synthesisstrategy=Vivado Synthesis Defaults implstrategy=Vivado Implementation Defaults currentsynthesisrun=synth_1 currentimplrun=impl_1
totalsynthesisruns=2 totalimplruns=2

unisim_transformation
pre_unisim_transformation
bufg=1 carry4=16 dsp48e1=1 fdre=110
fdse=1 gnd=5 ibuf=11 lut1=59
lut2=43 lut3=54 lut4=41 lut5=50
lut6=156 muxf7=1 obuf=32 vcc=4
xadc=1
post_unisim_transformation
bufg=1 carry4=16 dsp48e1=1 fdre=110
fdse=1 gnd=5 ibuf=11 lut1=59
lut2=43 lut3=54 lut4=41 lut5=50
lut6=156 muxf7=1 obuf=32 vcc=4
xadc=1

placer
usage
lut=273 ff=111 bram36=0 bram18=0
ctrls=4 dsp=1 iob=43 bufg=0
global_clocks=1 pll=0 bufr=0 nets=643
movable_instances=531 pins=3415 bogomips=0 effort=2
threads=2 placer_timing_driven=1 timing_constraints_exist=1 placer_runtime=11.842000

ip_statistics
xadc_wiz_v3_0/1
iptotal=1 component_name=xadc_wiz_0 enable_axi=false enable_axi4stream=false
dclk_frequency=100 enable_busy=true enable_convst=false enable_convstclk=false
enable_dclk=true enable_drp=true enable_eoc=true enable_eos=true
enable_vbram_alaram=false enable_vccddro_alaram=false enable_vccint_alaram=false enable_vccaux_alaram=false
enable_vccpaux_alaram=false enable_vccpint_alaram=false ot_alaram=false user_temp_alaram=false
timing_mode=continuous channel_averaging=None sequencer_mode=on startup_channel_selection=contineous_sequence

report_power
command_line_options
-verbose=default::[not_specified] -hier=default::power -no_propagation=default::[not_specified] -format=default::text
-file=[specified] -name=default::[not_specified] -xpe=default::[not_specified] -return_string=default::[not_specified]
-vid=default::[not_specified] -append=default::[not_specified] -l=default::[not_specified]
usage
customer=TBD customer_class=TBD flow_state=routed family=artix7
die=xc7a100tcsg324-1 package=csg324 speedgrade=-1 version=2014.4
platform=nt64 temp_grade=commercial process=typical simulation_file=None
netlist_net_matched=NA pct_clock_constrained=0.000000 pct_inputs_defined=9 user_junc_temp=25.7 (C)
ambient_temp=25.0 (C) user_effective_thetaja=4.6 airflow=250 (LFM) heatsink=medium (Medium Profile)
user_thetasa=4.6 (C/W) board_selection=medium (10"x10") board_layers=12to15 (12 to 15 Layers) user_thetajb=5.7 (C/W)
user_board_temp=25.0 (C) junction_temp=25.7 (C) input_toggle=12.500000 output_toggle=12.500000
bi-dir_toggle=12.500000 output_enable=1.000000 bidir_output_enable=1.000000 output_load=5.000000
ff_toggle=12.500000 ram_enable=50.000000 ram_write=50.000000 dsp_output_toggle=12.500000
set/reset_probability=0.000000 enable_probability=0.990000 toggle_rate=False signal_rate=False
static_prob=False read_saif=False on-chip_power=0.149427 dynamic=0.052200
effective_thetaja=4.6 thetasa=4.6 (C/W) thetajb=5.7 (C/W) off-chip_power=0.000000
clocks=0.001478 logic=0.005591 signals=0.007380 dsp=0.001003
i/o=0.034808 xadc=0.001940 devstatic=0.097227 vccint_voltage=1.000000
vccint_total_current=0.031165 vccint_dynamic_current=0.016056 vccint_static_current=0.015109 vccaux_voltage=1.800000
vccaux_total_current=0.019422 vccaux_dynamic_current=0.001272 vccaux_static_current=0.018150 vcco33_voltage=3.300000
vcco33_total_current=0.013823 vcco33_dynamic_current=0.009823 vcco33_static_current=0.004000 vcco25_voltage=2.500000
vcco25_total_current=0.000000 vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000 vcco18_voltage=1.800000
vcco18_total_current=0.000000 vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000 vcco15_voltage=1.500000
vcco15_total_current=0.000000 vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000 vcco135_voltage=1.350000
vcco135_total_current=0.000000 vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000 vcco12_voltage=1.200000
vcco12_total_current=0.000000 vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000 vccaux_io_voltage=1.800000
vccaux_io_total_current=0.000000 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccbram_voltage=1.000000
vccbram_total_current=0.000247 vccbram_dynamic_current=0.000000 vccbram_static_current=0.000247 mgtavcc_voltage=1.000000
mgtavcc_total_current=0.000000 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000 mgtavtt_voltage=1.200000
mgtavtt_total_current=0.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000 vccadc_voltage=1.800000
vccadc_total_current=0.020800 vccadc_dynamic_current=0.000800 vccadc_static_current=0.020000 confidence_level_design_state=High
confidence_level_clock_activity=High confidence_level_io_activity=Low confidence_level_internal_activity=Medium confidence_level_device_models=High
confidence_level_overall=Low

report_utilization
slice_logic
slice_luts_used=302 slice_luts_fixed=0 slice_luts_available=63400 slice_luts_util_percentage=0.47
lut_as_logic_used=302 lut_as_logic_fixed=0 lut_as_logic_available=63400 lut_as_logic_util_percentage=0.47
lut_as_memory_used=0 lut_as_memory_fixed=0 lut_as_memory_available=19000 lut_as_memory_util_percentage=0.00
slice_registers_used=111 slice_registers_fixed=0 slice_registers_available=126800 slice_registers_util_percentage=0.08
register_as_flip_flop_used=111 register_as_flip_flop_fixed=0 register_as_flip_flop_available=126800 register_as_flip_flop_util_percentage=0.08
register_as_latch_used=0 register_as_latch_fixed=0 register_as_latch_available=126800 register_as_latch_util_percentage=0.00
f7_muxes_used=1 f7_muxes_fixed=0 f7_muxes_available=31700 f7_muxes_util_percentage=<0.01
f8_muxes_used=0 f8_muxes_fixed=0 f8_muxes_available=15850 f8_muxes_util_percentage=0.00
slice_used=100 slice_fixed=0 slice_available=15850 slice_util_percentage=0.63
slicel_used=56 slicel_fixed=0 slicem_used=44 slicem_fixed=0
lut_as_logic_used=302 lut_as_logic_fixed=0 lut_as_logic_available=63400 lut_as_logic_util_percentage=0.47
using_o5_output_only_used=2 using_o5_output_only_fixed= using_o6_output_only_used=255 using_o6_output_only_fixed=
using_o5_and_o6_used=45 using_o5_and_o6_fixed= lut_as_memory_used=0 lut_as_memory_fixed=0
lut_as_memory_available=19000 lut_as_memory_util_percentage=0.00 lut_as_distributed_ram_used=0 lut_as_distributed_ram_fixed=0
lut_as_shift_register_used=0 lut_as_shift_register_fixed=0 lut_flip_flop_pairs_used=328 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_available=63400 lut_flip_flop_pairs_util_percentage=0.51 fully_used_lut_ff_pairs_used=58 fully_used_lut_ff_pairs_fixed=
lut_ff_pairs_with_unused_lut_used=28 lut_ff_pairs_with_unused_lut_fixed= lut_ff_pairs_with_unused_flip_flop_used=242 lut_ff_pairs_with_unused_flip_flop_fixed=
unique_control_sets_used=4 minimum_number_of_registers_lost_to_control_set_restriction_used=17(Lost)
memory
block_ram_tile_used=0 block_ram_tile_fixed=0 block_ram_tile_available=135 block_ram_tile_util_percentage=0.00
ramb36_fifo*_used=0 ramb36_fifo*_fixed=0 ramb36_fifo*_available=135 ramb36_fifo*_util_percentage=0.00
ramb18_used=0 ramb18_fixed=0 ramb18_available=270 ramb18_util_percentage=0.00
dsp
dsps_used=1 dsps_fixed=0 dsps_available=240 dsps_util_percentage=0.41
dsp48e1_only_used=1
clocking
bufgctrl_used=1 bufgctrl_fixed=0 bufgctrl_available=32 bufgctrl_util_percentage=3.12
bufio_used=0 bufio_fixed=0 bufio_available=24 bufio_util_percentage=0.00
mmcme2_adv_used=0 mmcme2_adv_fixed=0 mmcme2_adv_available=6 mmcme2_adv_util_percentage=0.00
plle2_adv_used=0 plle2_adv_fixed=0 plle2_adv_available=6 plle2_adv_util_percentage=0.00
bufmrce_used=0 bufmrce_fixed=0 bufmrce_available=12 bufmrce_util_percentage=0.00
bufhce_used=0 bufhce_fixed=0 bufhce_available=96 bufhce_util_percentage=0.00
bufr_used=0 bufr_fixed=0 bufr_available=24 bufr_util_percentage=0.00
specific_feature
bscane2_used=0 bscane2_fixed=0 bscane2_available=4 bscane2_util_percentage=0.00
capturee2_used=0 capturee2_fixed=0 capturee2_available=1 capturee2_util_percentage=0.00
dna_port_used=0 dna_port_fixed=0 dna_port_available=1 dna_port_util_percentage=0.00
efuse_usr_used=0 efuse_usr_fixed=0 efuse_usr_available=1 efuse_usr_util_percentage=0.00
frame_ecce2_used=0 frame_ecce2_fixed=0 frame_ecce2_available=1 frame_ecce2_util_percentage=0.00
icape2_used=0 icape2_fixed=0 icape2_available=2 icape2_util_percentage=0.00
pcie_2_1_used=0 pcie_2_1_fixed=0 pcie_2_1_available=1 pcie_2_1_util_percentage=0.00
startupe2_used=0 startupe2_fixed=0 startupe2_available=1 startupe2_util_percentage=0.00
xadc_used=1 xadc_fixed=1 xadc_available=1 xadc_util_percentage=100.00
primitives
lut6_used=156 lut6_functional_category=LUT fdre_used=110 fdre_functional_category=Flop & Latch
lut3_used=54 lut3_functional_category=LUT lut5_used=50 lut5_functional_category=LUT
lut2_used=43 lut2_functional_category=LUT lut4_used=41 lut4_functional_category=LUT
obuf_used=32 obuf_functional_category=IO carry4_used=16 carry4_functional_category=CarryLogic
ibuf_used=11 ibuf_functional_category=IO lut1_used=3 lut1_functional_category=LUT
xadc_used=1 xadc_functional_category=Others muxf7_used=1 muxf7_functional_category=MuxFx
fdse_used=1 fdse_functional_category=Flop & Latch dsp48e1_used=1 dsp48e1_functional_category=Block Arithmetic
bufg_used=1 bufg_functional_category=Clock
io_standard
diff_sstl15_r=0 hstl_ii=0 sstl15_r=0 lvttl=0
diff_sstl15=0 hstl_i=0 hsul_12=0 diff_mobile_ddr=0
lvcmos33=1 sstl135_r=0 lvcmos15=0 lvcmos18=0
mobile_ddr=0 lvcmos25=0 pci33_3=0 lvcmos12=0
diff_hsul_12=0 hstl_i_18=0 hstl_ii_18=0 sstl18_i=0
sstl18_ii=0 sstl15=0 sstl135=0 lvds_25=0
diff_hstl_i=0 rsds_25=0 diff_hstl_ii=0 tmds_33=0
diff_hstl_i_18=0 mini_lvds_25=0 diff_hstl_ii_18=0 ppds_25=0
diff_sstl18_i=0 diff_sstl18_ii=0 diff_sstl135=0 diff_sstl135_r=0
blvds_25=0

router
usage
lut=323 ff=111 bram36=0 bram18=0
ctrls=4 dsp=1 iob=43 bufg=0
global_clocks=1 pll=0 bufr=0 nets=643
movable_instances=531 pins=3415 bogomips=0 high_fanout_nets=0
effort=2 threads=2 router_timing_driven=1 timing_constraints_exist=1
congestion_level=0 estimated_expansions=523770 actual_expansions=949167 router_runtime=34.799000

synthesis
command_line_options
-part=xc7a100tcsg324-1 -name=default::[not_specified] -top=XADCdemo -include_dirs=default::[not_specified]
-generic=default::[not_specified] -verilog_define=default::[not_specified] -constrset=default::[not_specified] -seu_protect=default::none
-flatten_hierarchy=default::rebuilt -gated_clock_conversion=default::off -directive=default::default -rtl=default::[not_specified]
-bufg=default::12 -fanout_limit=default::10000 -shreg_min_size=default::3 -mode=default::default
-fsm_extraction=default::auto -keep_equivalent_registers=default::[not_specified] -resource_sharing=default::auto -control_set_opt_threshold=default::auto
usage
elapsed=00:00:32s memory_peak=652.637MB memory_gain=460.047MB hls_ip=0

xsim
command_line_options
-sim_mode=default::behavioral -sim_type=default::