Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
date_generatedThu Jan 08 15:27:27 2015 product_versionVivado v2014.3 (64-bit)
build_version1034051 os_platformWIN64
registration_id206924054_1777497009_210572043_840 tool_flowVivado
betaFALSE route_designTRUE
target_familyzynq target_devicexc7z020
target_packageclg484 target_speed-1
random_idc994f41142c3590e9ccaaccdb7d423f5 project_idb4bc3ddc32fc42fe8f5b65d51092b6e7
project_iteration0

user_environment
os_nameMicrosoft Windows 7 , 64-bit os_releaseService Pack 1 (build 7601)
cpu_nameIntel(R) Core(TM) i7-4600U CPU @ 2.10GHz cpu_speed2693 MHz
total_processors1 system_ram17.000 GB

vivado_usage
project_data
srcsetcount=5 constraintsetcount=1 designmode=RTL prproject=false
reconfigpartitioncount=0 reconfigmodulecount=0 hdproject=false partitioncount=0
synthesisstrategy=Vivado Synthesis Defaults implstrategy=Vivado Implementation Defaults currentsynthesisrun=synth_1 currentimplrun=impl_1
totalsynthesisruns=1 totalimplruns=1

unisim_transformation
pre_unisim_transformation
bufg=4 carry4=4 fdre=52 gnd=4
ibufds=1 lut1=16 lut2=9 lut3=10
lut4=15 lut5=12 lut6=28 mmcme2_adv=1
obuf=30 oddr=1 vcc=4
post_unisim_transformation
bufg=4 carry4=4 fdre=52 gnd=4
ibufds=1 lut1=16 lut2=9 lut3=10
lut4=15 lut5=12 lut6=28 mmcme2_adv=1
obuf=30 oddr=1 vcc=4

placer
usage
lut=60 ff=52 bram36=0 bram18=0
ctrls=4 dsp=0 iob=32 bufg=0
global_clocks=2 pll=0 bufr=0 nets=192
movable_instances=177 pins=901 bogomips=0 effort=2
threads=2 placer_timing_driven=1 timing_constraints_exist=1 placer_runtime=0.903000

report_power
command_line_options
-verbose=default::[not_specified] -hier=default::power -no_propagation=default::[not_specified] -format=default::text
-file=[specified] -name=default::[not_specified] -xpe=default::[not_specified] -return_string=default::[not_specified]
-vid=default::[not_specified] -append=default::[not_specified] -l=default::[not_specified]
usage
customer=TBD customer_class=TBD flow_state=routed family=zynq
die=xc7z020clg484-1 package=clg484 speedgrade=-1 version=2014.3
platform=nt64 temp_grade=commercial process=typical simulation_file=None
netlist_net_matched=NA pct_clock_constrained=0.000000 pct_inputs_defined=0 user_junc_temp=125.0 (C)
ambient_temp=25.0 (C) user_effective_thetaja=11.533192 airflow=250 (LFM) heatsink=none
user_thetasa=0.0 (C/W) board_selection=medium (10"x10") board_layers=8to11 (8 to 11 Layers) user_thetajb=7.4 (C/W)
user_board_temp=25.0 (C) junction_temp=125.0 (C) input_toggle=12.500000 output_toggle=12.500000
bi-dir_toggle=12.500000 output_enable=1.000000 bidir_output_enable=1.000000 output_load=5.000000
ff_toggle=12.500000 ram_enable=50.000000 ram_write=50.000000 dsp_output_toggle=12.500000
set/reset_probability=0.000000 enable_probability=0.990000 toggle_rate=False signal_rate=False
static_prob=False read_saif=False on-chip_power=17.795701 dynamic=16.754990
effective_thetaja=11.5 thetasa=0.0 (C/W) thetajb=7.4 (C/W) off-chip_power=0.000000
logic=0.351949 signals=0.324213 mmcm=1.783729 i/o=14.295099
devstatic=1.040711 vccint_voltage=1.000000 vccint_total_current=1.020462 vccint_dynamic_current=0.721922
vccint_static_current=0.298540 vccaux_voltage=1.800000 vccaux_total_current=1.672817 vccaux_dynamic_current=1.572578
vccaux_static_current=0.100238 vcco33_voltage=3.300000 vcco33_total_current=0.000000 vcco33_dynamic_current=0.000000
vcco33_static_current=0.000000 vcco25_voltage=2.500000 vcco25_total_current=5.281971 vcco25_dynamic_current=5.280971
vcco25_static_current=0.001000 vcco18_voltage=1.800000 vcco18_total_current=0.000000 vcco18_dynamic_current=0.000000
vcco18_static_current=0.000000 vcco15_voltage=1.500000 vcco15_total_current=0.000000 vcco15_dynamic_current=0.000000
vcco15_static_current=0.000000 vcco135_voltage=1.350000 vcco135_total_current=0.000000 vcco135_dynamic_current=0.000000
vcco135_static_current=0.000000 vcco12_voltage=1.200000 vcco12_total_current=0.000000 vcco12_dynamic_current=0.000000
vcco12_static_current=0.000000 vccaux_io_voltage=1.800000 vccaux_io_total_current=0.000000 vccaux_io_dynamic_current=0.000000
vccaux_io_static_current=0.000000 vccbram_voltage=1.000000 vccbram_total_current=0.026492 vccbram_dynamic_current=0.000000
vccbram_static_current=0.026492 mgtavcc_voltage=1.000000 mgtavcc_total_current=0.000000 mgtavcc_dynamic_current=0.000000
mgtavcc_static_current=0.000000 mgtavtt_voltage=1.200000 mgtavtt_total_current=0.000000 mgtavtt_dynamic_current=0.000000
mgtavtt_static_current=0.000000 mgtvccaux_voltage=1.800000 mgtvccaux_total_current=0.000000 mgtvccaux_dynamic_current=0.000000
mgtvccaux_static_current=0.000000 vccpint_voltage=1.000000 vccpint_total_current=0.472757 vccpint_dynamic_current=0.000000
vccpint_static_current=0.472757 vccpaux_voltage=1.800000 vccpaux_total_current=0.010330 vccpaux_dynamic_current=0.000000
vccpaux_static_current=0.010330 vccpll_voltage=1.800000 vccpll_total_current=0.003000 vccpll_dynamic_current=0.000000
vccpll_static_current=0.003000 vcco_ddr_voltage=1.500000 vcco_ddr_total_current=0.000000 vcco_ddr_dynamic_current=0.000000
vcco_ddr_static_current=0.000000 vcco_mio0_voltage=1.800000 vcco_mio0_total_current=0.000000 vcco_mio0_dynamic_current=0.000000
vcco_mio0_static_current=0.000000 vcco_mio1_voltage=1.800000 vcco_mio1_total_current=0.000000 vcco_mio1_dynamic_current=0.000000
vcco_mio1_static_current=0.000000 vccadc_voltage=1.800000 vccadc_total_current=0.020000 vccadc_dynamic_current=0.000000
vccadc_static_current=0.020000 confidence_level_design_state=High confidence_level_clock_activity=Low confidence_level_io_activity=Low
confidence_level_internal_activity=Medium confidence_level_device_models=High confidence_level_overall=Low

report_utilization
slice_logic
slice_luts_used=60 slice_luts_fixed=0 slice_luts_available=53200 slice_luts_util_percentage=0.11
lut_as_logic_used=60 lut_as_logic_fixed=0 lut_as_logic_available=53200 lut_as_logic_util_percentage=0.11
lut_as_memory_used=0 lut_as_memory_fixed=0 lut_as_memory_available=17400 lut_as_memory_util_percentage=0.00
slice_registers_used=52 slice_registers_fixed=0 slice_registers_available=106400 slice_registers_util_percentage=0.04
register_as_flip_flop_used=52 register_as_flip_flop_fixed=0 register_as_flip_flop_available=106400 register_as_flip_flop_util_percentage=0.04
register_as_latch_used=0 register_as_latch_fixed=0 register_as_latch_available=106400 register_as_latch_util_percentage=0.00
f7_muxes_used=0 f7_muxes_fixed=0 f7_muxes_available=26600 f7_muxes_util_percentage=0.00
f8_muxes_used=0 f8_muxes_fixed=0 f8_muxes_available=13300 f8_muxes_util_percentage=0.00
slice_used=24 slice_fixed=0 slice_available=13300 slice_util_percentage=0.18
slicel_used=15 slicel_fixed=0 slicem_used=9 slicem_fixed=0
lut_as_logic_used=60 lut_as_logic_fixed=0 lut_as_logic_available=53200 lut_as_logic_util_percentage=0.11
using_o5_output_only_used=0 using_o5_output_only_fixed= using_o6_output_only_used=42 using_o6_output_only_fixed=
using_o5_and_o6_used=18 using_o5_and_o6_fixed= lut_as_memory_used=0 lut_as_memory_fixed=0
lut_as_memory_available=17400 lut_as_memory_util_percentage=0.00 lut_as_distributed_ram_used=0 lut_as_distributed_ram_fixed=0
lut_as_shift_register_used=0 lut_as_shift_register_fixed=0 lut_flip_flop_pairs_used=72 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_available=53200 lut_flip_flop_pairs_util_percentage=0.13 fully_used_lut_ff_pairs_used=32 fully_used_lut_ff_pairs_fixed=
lut_ff_pairs_with_unused_lut_used=12 lut_ff_pairs_with_unused_lut_fixed= lut_ff_pairs_with_unused_flip_flop_used=28 lut_ff_pairs_with_unused_flip_flop_fixed=
unique_control_sets_used=4 minimum_number_of_registers_lost_to_control_set_restriction_used=20(Lost)
memory
block_ram_tile_used=0 block_ram_tile_fixed=0 block_ram_tile_available=140 block_ram_tile_util_percentage=0.00
ramb36_fifo*_used=0 ramb36_fifo*_fixed=0 ramb36_fifo*_available=140 ramb36_fifo*_util_percentage=0.00
ramb18_used=0 ramb18_fixed=0 ramb18_available=280 ramb18_util_percentage=0.00
dsp
dsps_used=0 dsps_fixed=0 dsps_available=220 dsps_util_percentage=0.00
clocking
bufgctrl_used=2 bufgctrl_fixed=0 bufgctrl_available=32 bufgctrl_util_percentage=6.25
bufio_used=0 bufio_fixed=0 bufio_available=16 bufio_util_percentage=0.00
mmcme2_adv_used=1 mmcme2_adv_fixed=0 mmcme2_adv_available=4 mmcme2_adv_util_percentage=25.00
plle2_adv_used=0 plle2_adv_fixed=0 plle2_adv_available=4 plle2_adv_util_percentage=0.00
bufmrce_used=0 bufmrce_fixed=0 bufmrce_available=8 bufmrce_util_percentage=0.00
bufhce_used=0 bufhce_fixed=0 bufhce_available=72 bufhce_util_percentage=0.00
bufr_used=0 bufr_fixed=0 bufr_available=16 bufr_util_percentage=0.00
specific_feature
bscane2_used=0 bscane2_fixed=0 bscane2_available=4 bscane2_util_percentage=0.00
capturee2_used=0 capturee2_fixed=0 capturee2_available=1 capturee2_util_percentage=0.00
dna_port_used=0 dna_port_fixed=0 dna_port_available=1 dna_port_util_percentage=0.00
efuse_usr_used=0 efuse_usr_fixed=0 efuse_usr_available=1 efuse_usr_util_percentage=0.00
frame_ecce2_used=0 frame_ecce2_fixed=0 frame_ecce2_available=1 frame_ecce2_util_percentage=0.00
icape2_used=0 icape2_fixed=0 icape2_available=2 icape2_util_percentage=0.00
startupe2_used=0 startupe2_fixed=0 startupe2_available=1 startupe2_util_percentage=0.00
xadc_used=0 xadc_fixed=0 xadc_available=1 xadc_util_percentage=0.00
primitives
fdre_used=52 fdre_functional_category=Flop & Latch obuf_used=30 obuf_functional_category=IO
lut6_used=28 lut6_functional_category=LUT lut4_used=15 lut4_functional_category=LUT
lut5_used=12 lut5_functional_category=LUT lut3_used=10 lut3_functional_category=LUT
lut2_used=9 lut2_functional_category=LUT lut1_used=4 lut1_functional_category=LUT
carry4_used=4 carry4_functional_category=CarryLogic bufg_used=2 bufg_functional_category=Clock
oddr_used=1 oddr_functional_category=IO mmcme2_adv_used=1 mmcme2_adv_functional_category=Clock
ibufds_used=1 ibufds_functional_category=IO
io_standard
diff_sstl18_ii=0 hstl_i=0 lvcmos12=0 sstl135_r=0
lvcmos18=0 mobile_ddr=0 lvttl=0 pci33_3=0
lvcmos33=0 diff_sstl15=0 hstl_ii=0 diff_mobile_ddr=0
hsul_12=0 lvcmos25=1 lvcmos15=0 hstl_i_18=0
diff_hsul_12=0 hstl_ii_18=0 sstl18_i=0 sstl18_ii=0
sstl15=0 sstl15_r=0 sstl135=0 lvds_25=1
diff_hstl_i=0 rsds_25=0 diff_hstl_ii=0 tmds_33=0
diff_hstl_i_18=0 mini_lvds_25=0 diff_hstl_ii_18=0 ppds_25=0
diff_sstl18_i=0 diff_sstl15_r=0 diff_sstl135=0 diff_sstl135_r=0
blvds_25=0

router
usage
lut=64 ff=52 bram36=0 bram18=0
ctrls=4 dsp=0 iob=32 bufg=0
global_clocks=2 pll=0 bufr=0 nets=192
movable_instances=177 pins=901 bogomips=0 high_fanout_nets=0
effort=2 threads=2 router_timing_driven=1 timing_constraints_exist=1
estimated_expansions=103326 actual_expansions=336461 router_runtime=33.433000

synthesis
command_line_options
-part=xc7z020clg484-1 -name=default::[not_specified] -top=Top -include_dirs=default::[not_specified]
-generic=default::[not_specified] -verilog_define=default::[not_specified] -constrset=default::[not_specified] -seu_protect=default::none
-flatten_hierarchy=default::rebuilt -gated_clock_conversion=default::off -directive=default::default -rtl=default::[not_specified]
-bufg=default::12 -fanout_limit=default::10000 -shreg_min_size=default::3 -mode=default::default
-fsm_extraction=default::auto -keep_equivalent_registers=default::[not_specified] -resource_sharing=default::auto -control_set_opt_threshold=default::auto
usage
elapsed=00:00:26s memory_peak=584.145MB memory_gain=400.359MB