Formerly known as Zmod DAC.
The Digilent Zmod AWG, is an open-source hardware SYZYGY™ 1) compatible pod containing a dual-channel DAC and the associated front end. The Zmod AWG is intended to be used with any SYZYGY™ compatible carrier board having the required capabilities.
The analog outputs can be connected to a circuit using SMA cables. Driven by the SYZYGY™ carrier, the Zmod AWG can generate two simultaneous signals (50Ω, ±5V, single-ended, 14-bit, 100MS/s, 40MHz+ bandwidth).
The Zmod AWG was designed to be a piece in a modular, HW and SW open-source ecosystem. Combined with a SYZYGY™ carrier, other SYZYGY™ compatible pods, Zmod AWG can be used for a variety of applications: data acquisition systems, closed loop controllers, etc.
This document describes the Zmod AWG's circuits, with the intent of providing a better understanding of its electrical functions, operations, and a more detailed description of the hardware’s features and limitations. It is not intended to provide enough information to enable complete duplication of the Zmod AWG, but can help users to design custom configurations for programmable parts in the design.
Zmod AWG's high-level block diagram is presented in Fig. 2 below. The core of the Zmod AWG is the dual channel, high speed, low power, 14-bit, 125MS/s DAC, AD9717. The carrier board is responsible to configure the internal registers of the DAC circuit, provide the acquisition clock and generate the data.
The Analog Output block is also called the AWG (Arbitrary Waveform Generator), because of similar structure and behavior to such a front end. The signals in this circuitry use “AWG” indexes, to indicate they are related to the AWG block. Signal and equations also use certain naming conventions. Analog voltages are prefixed with a “V” (for voltage), and suffixes and indexes are used in various ways: to specify the location in the signal path (OUT, DAC, etc.); to indicate the related instrument (AWG, etc.); and to indicate the channel (1 or 2). Referring to the block diagram in Fig. 2 below:
In the sections that follow, schematics are not shown separately for identical blocks. For example, the AWG I/V schematic is only shown for channel 1 since the schematic for channel 2 is identical. Indexes are omitted where not relevant. As examples, in equation \ref{2} below, $V_{outAWGFS}$ does not contain the channel index (because the equation applies to both channels 1 and 2).
Figure 2. Zmod AWG Block diagram.
As shown in Fig. 3, the reference voltage for the AWG is generated by IC42 (ADR3412ARJZ).
A divided version is provided to the DAC:
$$V_{REFIO\_AWG}=V_{REF1V2\_AWG} \cdot \frac{R_{27}}{R_{26}+{R_{27}}}=1V\label{1}\tag{1}$$
Figure 3. Reference voltage.
The Analog Devices AD9717 dual, low-power 14-bit TxDAC digital-to-analog converter is used to generate the wave. The main features are:
The parallel Data Bus, the single ended 100 MHz clock and the SPI configuration bus are driven by the SYZYGY™ carrier board FPGA. External VREFIO_AWG reference voltage is used. The Full Scale is set via the FSADJx pins. The ADG787 2.5Ω CMOS Low Power Dual 2:1 MUX/DEMUX is used to connect ${{\text{R}}_{set}}$ of either 8kΩ (for high gain) or 32kΩ (for low gain) from FSADJx pin to GND.
The Full Scale DAC output current is:
$$I_{outAWGFS}=32 \cdot \frac{V_{REFIO\_AWG}}{R_{set}}\label{2}\tag{2}$$
For high-gain (High Range):
$$I_{outAWGFS\_HG}=32 \cdot \frac{1V}{8.06k \Omega}=3.97mA\label{3}\tag{3}$$
For low-gain (Low Range):
$$I_{outAWGFS\_HG}=32 \cdot \frac{1V}{32k \Omega}=1mA\label{4}\tag{4}$$
The ADG787 features:
The AWG Out stage is the output stage of the AWG. It provides the 50ohm output impedance signal and protection to accidental shorts.
The output voltage range depends on High-gain versus Low-gain selection:
$$ - HighRange= - 5.32V < - 5V < V_{AWG\;REL\;HG} < 5V < 5.32V = HighRange $$ $$ -LowRange = - 1.33V < 1.25V < V_{AWG\;REL\;LG} < 1.25V < 1.33V = LowRange \label{10}\tag{10}$$
Only inner (tighter) ranges are used, for providing tolerance margins.
Low-gain is used to generate low amplitude signals with improved accuracy. Any amplitude of the output signal can be generated by combining LowGain/HighGain setting (rough) with the digital signal amplitude (fine).
With the 14-bit DAC, the absolute resolution of the AWG AC component is:
$$at\;Low\;Gain:\;\;\;\frac{{2*LowRange}}{{{2^{14}}}} ~= 167\mu V$$ $$at\;High\;Gain:\;\;\;\;\;\frac{{2*HighRange}}{{{2^{14}}}} ~= 665\mu V\label{11}\tag{11}$$
To generate a particular voltage value at the output of the AWG channel, the user application sends a signed 14 bit integer to the DAC. This value is computed as: $${N} = \frac{(V_{Out}-CA)}{(1+CG) \cdot (Range)}* (2^{13}-1)\in (-2^{13}, +2^{13}) \label{13}\tag{13}$$
were:
The IC7 relay (non-latching) is OPEN at the power-on, decoupling the power-on glitch of the OpAmp from the load. It is CLOSED by the FPGA, via Q1. R37 is a pull down when IC7 is OPEN and a dummy load when IC7 is CLOSED. D2 is an ESD suppressor.
R36 is the 50Ω AWG output impedance.
For low frequency range, the spectral characteristic was traced by a network analyzer function, with the Zmod AWG connected to a Zmod Scope, as shown in Fig. 7. Since the Zmod Scope BW is much wider, the overall system frequency characteristic represents the Zmod AWG characteristic. The BW is flat within 0.1dB up tp 10MHz+.
Figure 7. Low frequency AWG spectral characteristics
However, the figure Fig. 7 cannot show the high frequency range of the Zmod AWG BW: the Zmod AWG samples at 100MSPS, which removes the 50MHz spectral component and attenuates the nearby frequencies.
To trace the analog bandwidth of the DAC and output stage beyond the theoretical limit of fSAMPLE/2= 50MHz, the following experiment was performed:
The characteristic is shown in Fig. 8.
Figure 8. High Frequency AWG spectral characteristics (left), 1dB detail (right)
The 3dB bandwidth is 40MHz+, the 0.5dB bandwidth is 20MHz+, the ±0.1dB flatness band is 14MHz+.
The 3dB bandwidth is close to the theoretical Nyquist limit for a 100MHz sampling system. This has the advantage of very sharp edges (see the rectangular signal in Fig. 9), but also generates alias effects. The Zmod Scope generated signals were recorded with a high BW scope in Fig. 9, and the right side of Fig. 10 and Fig. 11. In Fig. 11, the sinus frequency is 10MHz, and the 100MHz samples are clearly visible. In the left side of Fig. 10 and Fig. 11, the same scope was used, but with 20MHz BW limitation. The rectangular signal edges are slower and the sine wave samples are not visible.
The typical Slew Rate of the AWG can be read in Fig. 9:
$$ SR=\frac{2.05V}{11.2ns}=183V/\mu S \label{18}\tag{18} $$
Figure 9. AWG rectangular signal (large signal)Figure 10. AWG rectangular signal (small signal); scope set at 20MHz BW limit (left), full BW (right)
Figure 11. AWG sinusoidal signal (smallsignal); scope set at 20MHz BW limit (left), full BW (right)
The ATtinny44 MCU works as a I2C memory, storing the SYZYGY™ DNA information and the Calibration Coefficients. The J5 connector is used for programming the MCU and the SYZYGY™ DNA at manufacturing.
The DNA and the Factory Calibration Coefficients are stored in the Flash memory of the MCU, which appears to the I2C interface as “read-only”. The User Calibration Coefficients are stored in the EEPROM memory of the MCU, which is write-protected via a magic number at a magic address. The memory structure can be consulted below.
Figure 12. The MCU
Table 1. The Flash memory structure
Address | Function | Size (Bytes) |
---|---|---|
0x8000 - 0x80FF | DNA | 256 |
0x8100 - 0x817F | Factory Calibration | 128 |
0x8180 - 0x83FF | Future use | 896 |
The Zmod AWG is compliant with SYZYGY™ Specification. It contains an MCU able to calculate the Geographical Address and provide the DNA information via I2C. The DNA is stored in the MCU FLASH at the address range: 0x8000 - 0x80FF with the following structure:
Table 2. The Zmod AWG DNA structure
Contents | Type | Size(Bytes) | Value | Address |
---|---|---|---|---|
DNA full data length | uint16 | 2 | 91 | 0x8000 |
DNA header length | uint16 | 2 | 40 | 0x8002 |
SYZYGY DNA major version | uint8 | 1 | 1 | 0x8004 |
SYZYGY DNA minor version | uint8 | 1 | 0 | 0x8005 |
Required SYZYGY DNA major version | uint8 | 1 | 1 | 0x8006 |
Required SYZYGY DNA minor version | uint8 | 1 | 0 | 0x8007 |
Maximum operating 5V load (mA) | uint16 | 2 | 600 | 0x8008 |
Maximum operating 3.3V load (mA) | uint16 | 2 | 1 | 0x800A |
Maximum VIO load (mA) | uint16 | 2 | 10 | 0x800C |
Attribute flags | uint16 | 2 | 0 | 0x800E |
Minimum operating VIO1 (10 mV steps) | uint16 | 2 | 180 | 0x8010 |
Maximum operating VIO1 (10 mV steps) | uint16 | 2 | 180 | 0x8012 |
Minimum operating VIO2 (10 mV steps) | uint16 | 2 | 170 | 0x8014 |
Maximum operating VIO2 (10 mV steps) | uint16 | 2 | 190 | 0x8016 |
Minimum operating VIO3 (10 mV steps) | uint16 | 2 | 0 | 0x8018 |
Maximum operating VIO3 (10 mV steps) | uint16 | 2 | 0 | 0x801A |
Minimum operating VIO4 (10 mV steps) | uint16 | 2 | 0 | 0x801C |
Maximum operating VIO4 (10 mV steps) | uint16 | 2 | 0 | 0x801E |
Manufacturer name length | uint8 | 1 | 12 | 0x8020 |
Product name length | uint8 | 1 | 13 | 0x8021 |
Product model / Part number length | uint8 | 1 | 13 | 0x8022 |
Product version / revision length | uint8 | 1 | 1 | 0x8023 |
Serial number length | uint8 | 1 | 12 | 0x8024 |
RESERVED | uint8 | 1 | 0 | 0x8025 |
CRC-16 (most significant byte) | uint8 | 1 | 0xA5 | 0x8026 |
CRC-16 (least significant byte) | uint8 | 1 | 0x1E | 0x8027 |
END DATA HEADER | ||||
Manufacturer name | string | 12 | Digilent Inc | 0x8028 |
Product name | string | 13 | Zmod AWG 1411 | 0x8034 |
Product model / Part number | string | 13 | Zmod AWG 1411 | 0x8041 |
Product version / revision | string | 1 | C | 0x804E |
Serial number | string | 12 | 210397000000 | 0x804F |
Product ID | uint32 | 4 | 0x80200300 | 0x80FC |
The analog circuitry described in previous chapters includes passive and active electronic components. The datasheet specs show parameters (resistance, capacitance, offsets, bias currents, etc.) as typical values and tolerances. The equations in previous chapters consider typical values. Component tolerances affect DC and AC performances of the Zmod AWG. To minimize these effects, the design uses:
A software calibration is performed on each device as a part of the manufacturing test. The AWG outputs are connected to calibrated voltmeters. A set of measurements is used to identify all the DC errors (Gain, Offset) of each analog stage. Correction (Calibration) parameters are computed and stored in the Calibration Memory, on the Zmod AWG device, both as Factory Calibration Data and User Calibration Data. The WaveForms software allows the user performing an in-house calibration and overwrite the User Calibration Data. Returning to Factory Calibration is always possible.
The Software reads the calibration parameters from the Zmod AWG MCU via the I2C bus and uses them to correct the generated signals. The structure of the data is shown below:
Table 3. The Calibration Data Structure
Heading 1 | Name | Size (Bytes) | Type | Flash Address (Factory Calibration) | EEPROM Address (User Calibration) |
---|---|---|---|---|---|
Magic ID | 1 | uchar 0xAD | 0x8100 | 0x7000 | |
Calibration Time | 4 | unix timestamp | 0x8101 | 0x7001 | |
Channel 1 LG Gain | CG | 4 | float32 | 0x8105 | 0x7005 |
Channel 1 LG Offset | CA | 4 | float32 | 0x8109 | 0x7009 |
Channel 1 HG Gain | CG | 4 | float32 | 0x810D | 0x700D |
Channel 1 HG Offset | CA | 4 | float32 | 0x8111 | 0x7011 |
Channel 2 LG Gain | CG | 4 | float32 | 0x8115 | 0x7015 |
Channel 2 LG Offset | CA | 4 | float32 | 0x8119 | 0x7019 |
Channel 2 HG Gain | CG | 4 | float32 | 0x811D | 0x701D |
Channel 2 HG Offset | CA | 4 | float32 | 0x8121 | 0x7021 |
Channel 1 Linearity | 34 | uchar | 0x8125 | 0x7025 | |
Channel 2 Linearity | 34 | uchar | 0x8147 | 0x7047 | |
Log | 22 | string | 0x8169 | 0x7069 | |
CRC | 1 | uchar | 0x817F | 0x707F |
Table 4. The EEPROM Memory Map
Address | Function | Size (Bytes) |
---|---|---|
0x7000 - 0x707F | User Calibration | 128 |
0x7080 - 0x70FF | Future Use | 128 |
At the power up the EEPROM memory is protected against write operations. To disable the write protection one has to write a magic number to a magic address over I2C. To re-enable the write protection one has to write a any other number to the magic address.
Table 5. The Write Protection Disable magic number and address
Magic Number | Magic Address |
---|---|
0xD2 | 0x6FFF |
This block includes the internal power supplies.
The Zmod AWG gets the digital rails from the carrier board, via the SYZYGY™ connector:
The internal analog rails sequence is:
The analog supply AVCC3V3 is built from VCC5V0 using IC10, an ADP122 5.5 V Input, 300 mA, Low Quiescent Current, CMOS Linear Regulator, Fixed Output Voltage. To reduce noise in the I/V stage, the rail uses the LC filter: FB5 in Fig. 5.
The AVCC-2V5 analog power supply is implemented with the ADP2301 Step-Down regulator in an inverting Buck-Boost configuration. See application Note AN-1083: Designing an Inverting Buck Boost Using the ADP2300 and ADP2301. To reduce noise and reduce the crosstalk between supplied circuits, the rail uses the LC filter: FB3 in Fig. 5.. The ADP2301 features:
The output voltage is:
$$V_{OUT}=-V_{FB} \cdot \frac{R_{49}+R_{50}}{R_{50}}=-2.5V\label{19}\tag{19}$$
Where:
$${V_{FB}} = 0.8V\;typical\label{20}\tag{20}$$
The user power supplies Fig. 15 use ADP1612 Switching Converter in SEPIC DC-to-DC topology. Main features:
The output voltage is:
$$V_{OUT}=V_{FB} \cdot \frac{R_{80}+R_{84}}{R_{84}}=8.538V\label{21}\tag{21}$$
Where:
$${V_{FB}} = 1.235V\;typical\label{22}\tag{22}$$
The supply is enabled after VCC5V0 and AVCC3V3 (see EN_AVCC in Fig. 16)
The user power supplies Fig. 16 use ADP1612 Switching Converter in CUK DC-to-DC topology.
IC13 introduces the required inversion for the negative supply. ADA4841 features:
The output voltage is:
$$V_{AVCC8V0}=-V_{FB} \cdot \frac{R_{56}}{R_{60}}=-8.035V\label{23}\tag{23}$$
Where:
$${V_{FB}} = 1.235V\;typical\label{24}\tag{24}$$
The supply is enabled after VCC5V0 and AVCC3V3.
The SYZYGY™ connector in provides the interface with the carrier board. The used signals are:
Table 6. The SYZYGY™ compatibility table
Parameter | Value |
---|---|
Maximum 5V supply current | 600mA |
Maximum 3.3V supply current | 1mA |
VIO supply voltage | 1.8V |
Maximum VIO supply current | 10mA |
Total number of I/O | 21 |
Number of differential I/O pairs | 0 |
Width | Single |
Written by Mircea Dabacan, PhD, Technical University of Cluj-Napoca Romania