====== Analog Discovery 2 Hardware Design Guide ====== ~~TechArticle~~ The Analog Discovery 2 is equipped with 13 test and measurement instruments providing the functionality of an entire benchtop worth of equipment in one device. The Oscilloscope, Waveform Generator, Logic Analyzer, Protocol Analyzer, Spectrum Analyzer, Power Supplies, and more provide a device that can become a pop-up electronics laboratory anywhere. The physical design of the Analog Discovery 2 provides BNC connectors or MTE cables for the analog inputs and outputs, MTE cables for the digital I/O, triggers, and power supplies, and a large removable and breadboardable design surface supporting a large variety of designs or projects. This document, the hardware design guide, describes the architecture and implementation of many of the key circuits and features of the Analog Discovery 2. Those users looking for deep and detailed information on the operation of their device may find this of particular interest. For a summary of the key specifications of the device, check out the [[specifications]]. For a high-level overview of the key features of the device, check out the [[reference-manual]]. ---- ===== Pinout Diagram ===== For reference, the pinout of the Analog Discovery 2 is presented in Figure 1. {{ :analog_discovery_2:analogdiscovery2-pinout-600.png?nolink&450 |Analog Discovery 2 Pinout Diagram.}} //{{anchor:figure_1:Figure 1. Analog Discovery 2 Pinout Diagram.}}// ---- ===== 1.1 Architectural Overview and Block Diagram ===== Analog Discovery 2's high-level block diagram is presented in [[analog_discovery_2:refmanual#figure_2|Fig. 2]] below. The core of the Analog Discovery 2 is the [[https://www.xilinx.com/|Xilinx®]] [[https://www.xilinx.com/products/silicon-devices/fpga/spartan-6.html|Spartan®-6]] FPGA (specifically, the XC6SLX16-1L device). The WaveForms application automatically programs the Discovery’s FPGA at start-up with a configuration file designed to implement a multi-function test and measurement instrument. Once programmed, the FPGA inside the Discovery communicates with the PC-based WaveForms application via a USB 2.0 connection. The WaveForms software works with the FPGA to control all the functional blocks of the Analog Discovery 2, including setting parameters, acquiring data, and transferring and storing data. Signals in the **Analog Input** block, also called the **Scope**, use "SC" indexes to indicate they are related to the scope block. Signals in the **Analog Output** block, also called **AWG**, use “AWG” indexes, and signals in the **Digital** block use a **D** index – all of the instruments offered by the Discovery 2 and WaveForms use the circuits in these three blocks. Signal and equations also use certain naming conventions. Analog voltages are prefixed with a "V" (for voltage), and suffixes and indexes are used in various ways: to specify the location in the signal path (IN, MUX, BUF, ADC, etc.); to indicate the related instrument (SC, AWG, etc.); to indicate the channel (1 or 2); and to indicate the type of signal (P, N, or diff). Referring to the block diagram in [[analog_discovery_2:refmanual#figure_2|Fig. 2]] below: * The** Analog Inputs/Scope** instrument block includes: * **Input Divider and Gain Control**: high bandwidth input adapter/divider. High or low-gain can be selected by the FPGA * **Buffer**: high impedance buffer * **Driver**: provides appropriate signal levels and protection to the ADC. Offset voltage is added for vertical position setting * **Scope Reference and Offset**: generates and buffers reference and offset voltages for the scope stages * **ADC**: the analog-to-digital converter for both scope channels. * The **Arbitrary Outputs/AWG** instrument block includes: * **DAC**: the digital-to-analog converter for both AWG channels * **I/V**: current to bipolar voltage converters * **Out**: output stages * **Audio**: audio amplifiers for headphone * A precision **Oscillator** and a **Clock Generator** provide a high quality clock signal for the AD and DA converters. * The **Digital I/O** block exposes protected access to the FPGA pins assigned for the Digital Pattern Generator and Logic Analyzer. * The **Power Supplies and Control** block generates all internal supply voltages as well as user supply programmable voltages. The control block also monitors the device power consumption for USB compliance when power is supplied via the USB connection. When external power supply is used, the control block allows more power for the user supplies. Under the FPGA control, power for unused functional blocks can be turned off. * The **USB Controller** interfaces with the PC for programming the volatile FPGA memory after power on or when a new configuration is requested. After that, it performs the data transfer between the PC and FPGA. * The **Calibration Memory** stores all calibration parameters. Except for the “Probe Calibration” trimmers in the scope Input divider, the Analog Discovery 2 includes no analog calibration circuitry. Instead, a calibration operation is performed at manufacturing (or by the user), and parameters are stored in memory. The WaveForms software uses these parameters to correct the acquired data and the generated signals In the sections that follow, schematics are not shown separately for identical blocks. For example, the Scope Input Divider and Gain Selection schematic is only shown for channel 1 since the schematic for channel 2 is identical. Indexes are omitted where not relevant. As examples, in equation \ref{4} below, $V_{in diff}$ does not contain the instrument index (which by context is understood to be the Scope), nor the channel index (because the equation applies to both channels 1 and 2). In equation \ref{3}, the type index is also missing because $V_{mux}$ and $V_{in}$ refer to any of //P// (positive), //N// (negative) or //diff// (differential) values. {{ :analog_discovery_2:figure_2.png |Figure 2. Analog Discovery 2 block diagram.}} //{{anchor:figure_2:Figure 2. Analog Discovery 2 block diagram.}}// ---- ===== 2. Scope ===== //**Important Note**: Unlike traditional inexpensive scopes, the Analog Discovery 2 inputs are fully differential. However, a GND connection to the circuit under test is needed to provide a stable common mode voltage. The Analog Discovery 2 GND reference is connected to the USB GND. Depending on the PC powering scheme, and other PC connections (Ethernet, audio, etc. – which might also be grounded) the Analog Discovery 2 GND reference might be connected to the whole GND system and ultimately to the power network protection (earth ground). The circuit under test might also be connected to earth or possibly floating. For safety reasons, it is the user’s responsibility to understand the powering and grounding scheme and make sure that there is a common GND reference between the Analog Discovery 2 and the circuit under test, and that the common mode and differential voltages do not exceed the limits shown in equation \ref{1}. Furthermore, for distortion-free measurements, the common mode and differential voltages need to fit into the linear range shown in Figs. [[analog_discovery_2:refmanual#figure_12|12]] and [[analog_discovery_2:refmanual#figure_13|13]]. For those applications which scope GND cannot be the USB ground, a USB isolation solution, such as what is described in ADI’s [[http://www.analog.com/en/circuits-from-the-lab/CN0160/vc.html|CN-0160]] can be used; however, this will limit things to USB full speed (12 Mbps), and will impact the update rate (screen refresh rates, not sample rates) of the Analog Discovery 2.// ===== 2.1. Scope Input Divider and Gain Selection ===== [[analog_discovery_2:refmanual#figure_3|Figure 3]] shows the scope input divider and gain selection stage. Two symmetrical R-C dividers provide: * Scope input impedance = 1MOhm || 24pF * Two different attenuations for high-gain/low-gain (10:1) * Controlled capacitance, much higher than the parasitical capacitance of subsequent stages * Constant attenuation and high CMMR over a large frequency range (trimmer adjusted) * Protection for overvoltage (with the ESD diodes of the ADG612 inputs) The maximum voltage rating for scope inputs is limited by C1 thru C24 to: $$-50V Racing -> External** modes. Running instruments are not affected, except User Supplies get more available power. However, removing the external power supply during **External** mode is not seamless. Only the USB controller keeps working (as supplied from the USB port). The FPGA gets unpowered and loses configuration data. The device stops all the instruments, EN_VBUS go HiZ, which leads to the **USB OFF** mode. WaveForms will prompt the user to select the device, which will re-program the FPGA. All the instruments can then be run, in the **USB** mode. An [[http://www.analog.com/en/power-management/power-monitors/adm1177/products/product.html|ADM1177]] Hot Swap Controller and Digital Power Monitor with Soft Start Pin is used to provide USB power compliance during **USB** and **Racing** modes [[analog_discovery_2:refmanual#figure_23|(IC21 in Fig. 23)]]. Remarkable ADM1177 features are: * Safe live board insertion and removal * Supply voltages from 3.15 V to 16.5 V * Precision current sense amplifier * 12-bit ADC for current and voltage read * Adjustable analog current limit with circuit breaker * ±3% accurate hot swap current limit level * Fast response limits peak fault current * Automatic retry or latch-off on current fault * Programmable hot swap timing via TIMER pin * Soft start pin for reference adjustment and programming of initial current ramp rate * I2C fast mode-compliant interface (400 kHz maximum) When enabled, (in **USB** or **Racing** modes), IC21 limits the current consumed from the USB port to: $${I_{limit}} = \frac{{100mV}}{{{R_{173}}}} = \frac{{100mV}}{{0.1\Omega }} = 1A\label{46}\tag{46}$$ For a maximum time of: $$t_{fault}=21.7 \left[ ms / \mu F \right] \cdot C_{80}=21.7 \left[ ms / \mu F \right] \cdot 0.47\mu F =10.2ms\label{47}\tag{47}$$ If the consumed current does not fall below ${I_{limit}}$ before ${t_{fault}}$, IC21 turns off Q2A. A hot swap retry is initiated after: $$t_{cool}=550 \left[ ms / \mu F \right] \cdot C_{80} = 550 \left[ \frac{ms}{\mu F} \right] \cdot 0.47 \mu F = 258.5ms\label{48}\tag{48}$$ To avoid high inrush currents at hot swap, Soft Start circuitry limits the current slope to: $$\frac {dI_{limit}}{dt} = \frac {10 \mu A}{C_{81}} \cdot \frac {1}{10 \cdot R_{173}} =212 \frac {mA}{ms} \label{49}\tag{49}$$ If the current drops below $\;{I_{limit}}$ before ${t_{fault}}$, normal operation begins. Similarly, IC26 (in **Racing** or **External** modes), limits the current consumed from the external power supply to: $${I_{limit}} = \frac {100mV}{R_{247}} = \frac {100mV}{0.036 \Omega} = 2.78A\label{50}\tag{50}$$ ${t_{fault}}$ and ${t_{cool}}$ are same as for IC21, and the current slope limit is: $$\frac {dI_{limit}}{dt} = \frac{10\mu A}{C_{432}} \cdot \frac{1}{10 \cdot R_{247}}=591 \frac{mA}{ms}\label{51}\tag{51}$$ The Analog Discovery 2 user pins are overvoltage protected. Overvoltage (or ESD) diodes short when a user pin is overdriven by the external circuitry (Circuit Under Test), back powering the input/output block and all the circuits sharing the same internal power supply. If the back-powered energy is higher than the used energy, the bi-directional power supply recovers the difference and delivers it to the previous node in the power chain. Eventually, the back-powering energy could arrive to the USB VBUS, raising the voltage above the 5V nominal value. D28 in [[analog_discovery_2:refmanual#figure_23|Fig. 23]] protects the PC USB port against such a situation. ---- ===== 6.2. Analog Supplies Control ===== During **USB** mode, the FPGA constantly reads from IC21 the current value through R173. (Optionally displayed on Main Window/Discovery or Status button). A warning is generated when exceeding 500mA (Status: OC = Over Current). If a value of 600mA is reached and Overcurrent protection is enabled (MainWindow/Device/Settings/Overcurrent protection), WaveForms turns off IC20 (ADP197) shown in [[analog_discovery_2:refmanual#figure_24|Fig. 24]] and IC27 shown [[analog_discovery_2:refmanual#figure_25|Fig. 25]], disabling the analog blocks and user power supplies. [[http://www.analog.com/en/switchesmultiplexers/analog-switches/adp197/products/product.html|ADP197]] main features: * Low RDSon of 12mΩ * Low input voltage range: 1.8V to 5.5V * 1.2V logic compatible enable logic * Overtemperature protection * Ultra-small 1.0mmX1.5mm, 6 ball, 0.5mm pitch WLCSP {{ :analog_discovery_2:figure_24.png |Figure 24. Analog Supplies control.}} //{{anchor:figure_24:Figure 24. Analog Supplies control.}}// ---- ===== 6.3. User Supplies Control ===== IC27 in [[analog_discovery_2:refmanual#figure_25|Fig. 25]] controls the power available for the user supplies. [[http://www.analog.com/en/products/power-management/power-monitors/hot-swap-power-monitors-ic/adm1270.html|ADM1270]] was selected for its main features: * Controls supply voltages from 4 V to 60 V * Gate drive for low voltage drop reverse supply protection * Gate drive for P-channel FETs * Inrush current limiting control * Adjustable current limit * Foldback current limiting * Automatic retry or latch-off on current fault * Programmable current-limit timer for safe operating area (SOA) * Power-good and fault outputs * Analog undervoltage (UV) and overvoltage (OV) protection * 16-lead 3x3mm LFCSP package * 16-lead QSOP package {{ :analog_discovery_2:figure_25.png |Figure 25. User supplies control.}} //{{anchor:figure_25:Figure 25. User supplies control.}}// IC27 limits the current consumed by both user power supplies together. The WaveForms software commands the FPGA to change the limit, depending on the power mode. During **USB** and **Racing** modes, SET_ILIM_USR pin is driven LOW by the FPGA. The voltage at the ISET pin of IC27 is: $${V_{Iset}} = \frac{{\frac{{{V_{cap}}}}{{{R_{253}}}}}}{{\frac{1}{{{R_{253}}}} + \frac{1}{{{R_{254}}}} + \frac{1}{{{R_{255}}}}}} = \frac{{\frac{{3.6V}}{{10k\Omega }}}}{{\frac{1}{{10k\Omega }} + \frac{1}{{1.74k\Omega }} + \frac{1}{{22.6k\Omega }}}} = 0.5V\label{52}\tag{52}$$ The current limit is set to: $$I_{limit}= \frac{V_{Iset}}{40 \cdot R_{21}} = \frac{0.5V}{40 \cdot 0.043 \Omega} = 290mA\label{53}\tag{53}$$ During **External** and **OFF** modes, SET_ILIM_USR pin is driven HiZ by the FPGA. The voltage at the ISET pin of IC27 is: $$V_{Iset}= \frac {V_{cap} \cdot R_{255}}{R_{253} + R_{255}} = \frac{3.6V \cdot 22.6k \Omega }{10k \Omega + 22.6k \Omega} = 2.5V\label{54}\tag{54}$$ The current limit is set to: $$I_{limit}= \frac {V_{Iset}}{40 \cdot R_{21}} = \frac {2.5V}{40 \cdot 0.043 \Omega} = 1.45A\label{55}\tag{55}$$ In both cases, ${I_{limit}}$ **is allowed** for a maximum time of: $$t_{fault}=21.7 \left[ ms / \mu F \right] \cdot C_{170} = 21.7 \left[ ms / \mu F \right] \cdot 4.7 \mu F = 102ms\label{56}\tag{56}$$ If the consumed current does not fall below ${I_{limit}}$ before ${t_{fault}}$, IC21 turns off Q2. A hot swap retry is initiated after: $$t_{cool}=550 \left[ ms / \mu F \right] \cdot C_{80} = 550 \left[ ms / \mu F \right] \cdot 4.7 \mu F = 2.585s\label{57}\tag{57}$$ Soft Start is not used; C183 is a No Load. If the current drops below ${I_{limit}}$ before ${t_{fault}}$, normal operation begins. The current limited by equations \ref{53} and \ref{55} is shared by both positive and negative user power supplies. After considering the efficiency of the user supply stages, about 100mA is available for user in both supplies together, in **USB Only** mode. In **External** mode, the current/power limit for user is set in the User Voltage Supplies, as explained below. ---- ===== 6.4. User Voltage Supplies ===== The user power supplies [[analog_discovery_2:refmanual#figure_26|(Fig. 26)]] use ADP1612 Switching Converter in Buck-Boost DC-to-DC topology. Main features: * 1.4A current limit * Minimum input voltage 1.8V * Pin-selectable 650 kHz or 1.3 MHz PWM frequency * Adjustable output voltage up to 20 V * Adjustable soft start * Undervoltage lockout IC46A/B op amps insert the command voltages $V_{SET+\_USR}$ and $V_{SET-\_USR}$, respectively, in the feedback loop. Additionally, IC46B introduces the required inversion for the negative supply. {{ :analog_discovery_2:ad2_27.png |Figure 26. User power supplies.}} //{{anchor:figure_26:Figure 26. User power supplies.}}// Since the op amps are included in negative feedback loops, the input pins voltages are equal: $${V_{ + IC46A}} = \frac{{\frac{{{V_{OUT + \_USR}}}}{{{R_{188}}}} + \frac{{{V_{SET + \_USR}}}}{{{R_{193}}}}}}{{\frac{1}{{{R_{188}}}} + \frac{1}{{{R_{193}}}}}} = {V_{ - IC46A}} = \frac{{\frac{{{V_{FB}}}}{{{R_{266}}}}}}{{\frac{1}{{{R_{265}}}} + \frac{1}{{{R_{266}}}}}}\label{58}\tag{58}$$ $${V_{ + IC46B}} = \frac{{\frac{{{V_{OUT - \_USR}}}}{{{R_{187}}}} + \frac{{{V_{FB}}}}{{{R_{270}}}}}}{{\frac{1}{{{R_{187}}}} + \frac{1}{{{R_{270}}}}}} = {V_{ - IC46B}} = \frac{{\frac{{{V_{SET - \_USR}}}}{{{R_{190}}}}}}{{\frac{1}{{{R_{72}}}} + \frac{1}{{{R_{190}}}}}}\label{59}\tag{59}$$ The input impedances for the op amps are matched: $$\frac{1}{{{R_{188}}}} + \frac{1}{{{R_{193}}}} = \frac{1}{{{R_{265}}}} + \frac{1}{{{R_{266}}}}\label{60}\tag{60}$$ $$\frac{1}{{{R_{187}}}} + \frac{1}{{{R_{270}}}} = \frac{1}{{{R_{72}}}} + \frac{1}{{{R_{190}}}}\label{61}\tag{61}$$ The user voltages are: $$V_{OUT\;+\_USR}=V_{FB} \cdot \frac{R_{188}}{R_{266}} - V_{SET\;+\_USR} \cdot \frac{R_{188}}{R_{193}}=5.33V-4.87 \cdot V_{SET\;+\_USR}\label{62}\tag{62}$$ $$V_{OUT\;-\_USR}=-V_{FB} \cdot \frac{R_{187}}{R_{270}} + V_{SET\;-\_USR} \cdot \frac{R_{187}}{R_{190}}=-5.33V+4.87 \cdot V_{SET\;-\_USR}\label{63}\tag{63}$$ Where: $${V_{FB}} = 1.235V\;typical\label{64}\tag{64}$$ IC43 [[analog_discovery_2:refmanual#figure_18|(Fig. 18)]] generates the setting voltages in the range: $$0 < V_{SET + \_USR},\; V_{SET - \_USR} < 1.2V\label{65}\tag{65}$$ Which would allow output voltages to be set in the ranges: $$ - 0.51V \le {V_{SET + \_USR}} < 5.33V\label{66}\tag{66}$$ $$0.51V \ge \; V_{SET - \_USR} > - 5.33V\label{67}\tag{67}$$ The margins allow for compensating the components’ tolerances. After calibration, the WaveForms SW only allows the ranges 0 to +/-5V respectively. Even so, output voltages below absolute value of 0.5V are not guaranteed. With light loads, such voltages might exhibit significant ripple (~15mV). Each supply can be disabled by the FPGA. ---- ===== 6.5. Internal Power Supplies===== ==== 6.5.1. Analog Supplies ==== Analog supplies need to have very low ripple to prevent noise from coupling into analog signals. Ferrite beads are used to filter the remaining switching noise and to separate the power supplies that go to the main analog circuit blocks, to avoid crosstalk. The 3.3V [[analog_discovery_2:refmanual#figure_27|(Fig. 27)]] and 1.8V [[analog_discovery_2:refmanual#figure_28|Fig. 28]] analog power supplies are implemented around an [[http://www.analog.com/en/power-management/switching-regulators-integrated-fet-switches/adp2138/products/product.html|ADP2138]] Fixed Output Voltage, 800mA, 3MHz, Step-Down DC-to-DC converter. To insure low output voltage ripple a second LC filter is added and forced PWM mode is selected. * Input voltage: 2.3 V to 5.5 V * Peak efficiency: 95% * 3 MHz fixed frequency operation * Typical quiescent current: 24 μA * Very small solution size * 6-lead, 1 mm × 1.5 mm WLCSP package * Fast load and line transient response * 100% duty cycle low dropout mode * Internal synchronous rectifier, compensation, and soft start * Current overload and thermal shutdown protections * Ultra-low shutdown current: 0.2 μA (typical) * Forced PWM and automatic PWM/PSM modes {{ :analog_discovery_2:ad2_28.png |Figure 27. 3.3V internal analog power supply.}} //{{anchor:figure_27:Figure 27. 3.3V internal analog power supply.}}// {{ :analog_discovery_2:ad2_29.png |Figure 28. 1.8V internal analog power supply.}} //{{anchor:figure_28:Figure 28. 1.8V internal analog power supply.}}// The -3.3V analog power supply [[analog_discovery_2:refmanual#figure_29|(Fig. 29)]] is implemented with the [[http://www.analog.com/en/power-management/switching-regulators-integrated-fet-switches/adp2301/products/product.html|ADP2301]] Step-Down regulator in an inverting Buck-Boost configuration. See application Note [[http://www.analog.com/static/imported-files/application_notes/AN-1083.pdf|AN-1083: Designing an Inverting Buck Boost Using the ADP2300 and ADP2301]]. The ADP2301 features: * 1.2 A maximum load current * ±2% output accuracy over temperature range * 1.4 MHz switching frequency * High efficiency up to 91% * Current-mode control architecture * Output voltage from 0.8 V to 0.85 × VIN * Automatic PFM/PWM mode switching * Integrated high-side MOSFET and bootstrap diode, * Internal compensation and soft start * Undervoltage lockout (UVLO), Overcurrent protection (OCP) and thermal shutdown (TSD) * Available in ultrasmall, 6-lead TSOT package {{ :analog_discovery_2:figure_29.png |Figure 29. -3.3V internal analog power supply.}} //{{anchor:figure_29:Figure 29. -3.3V internal analog power supply.}}// The Output voltage is set with an external resistor divider from Vout to FB: $$\frac{{{R_{180}}}}{{{R_{181}}}} = \;\frac{{ - {V_{out}} - {V_{ref}}}}{{{V_{ref}}}}\label{68}\tag{68}$$ Choosing $R_{181} = 10.2k{\text{\Omega }}$: $$R_{180}= \frac{3.3V-0.8V}{0.8V} \cdot 10.2k \Omega = 31.87k \Omega \label{69}\tag{69}$$ Closest standard value is $R_{180} = 31.6k{\text{\Omega }}$ The 5.5V and -5.5V supplies [[analog_discovery_2:refmanual#figure_30|Fig. 30]] are created with a Sepic-Cuk topology, built around a single [[http://www.analog.com/en/power-management/switching-regulators-integrated-fet-switches/adp1612/products/product.html|ADP1612]] Step-Up DC-to DC converter. Both Sepic and Cuk converters are connected to the same switching pin of the regulator. Only the positive Sepic output is regulated, while the negative output tracks the positive one. This is an accepted behavior, since similar load currents are expected on both positive and negative rails. {{ :analog_discovery_2:ad2_31.png |Figure 30. ±5.5V internal analog supplies.}} //{{anchor:figure_30:Figure 30. ±5.5V internal analog supplies.}}// The output current in a Sepic is discontinuous which results in a higher output ripple. To lower this ripple an additional output filter is added to the positive rail. For more information see application note: [[http://www.analog.com/static/imported-files/application_notes/AN-1106.pdf|AN-1106: An Improved Topology for Creating Split Rails from a Single Input Voltage]]. Setting the Output Voltage: $$\frac{{{R_{184}}}}{{{R_{185}}}} = \;\frac{{{V_{out}} - {V_{ref}}}}{{{V_{ref}}}}\label{70}\tag{70}$$ Choosing ${R_{185}} = 13.7k\Omega$: $$R_{184}= \frac{5.5V-1.235V}{1.235V} \cdot 13.7k \Omega = 47.31k \Omega\label{71}\tag{71}$$ Closest standard value is ${R_{184}} = 47.5k\Omega$ ==== 6.5.2. Digital Supplies ==== The 1V digital supply [[analog_discovery_2:refmanual#figure_31|(Fig. 31)]] is implemented with the [[http://www.analog.com/en/power-management/switching-regulators-integrated-fet-switches/adp2120/products/product.html|ADP2120-1]]. It has a fixed 1V output voltage option and a ±1.5% output accuracy which makes it suitable for the FPGA internal power supply. It also features: * 1.25A continuous output current * 145 mΩ and 70 mΩ integrated MOSFETs * Input voltage range from 2.3 V to 5.5 V; output voltage from 0.6 V to VIN * 1.2 MHz fixed switching frequency; Selectable PWM or PFM mode operation * Current mode architecture * Integrated soft start; Internal compensation * UVLO, OVP, OCP, and thermal shutdown * 10-lead, 3 mm × 3 mm LFCSP_WD package {{ :analog_discovery_2:figure_31.png |Figure 31. 1V internal digital supply.}} //{{anchor:figure_31:Figure 31. 1V internal digital supply.}}// The 3.3V digital supply [[analog_discovery_2:refmanual#figure_32|(Fig. 32)]] uses [[http://www.analog.com/en/power-management/switching-regulators-integrated-fet-switches/adp2503/products/product.html|ADP2503-3.3]] 600mA, 2.5MHz Buck-Boost DC-to-DC Converter: * Seamless transition between modes * 38 μA typical quiescent current * 2.5 MHz operation enables 1.5 μH inductor * Input voltage: 2.3 V to 5.5 V; * Fixed output voltage: 3.3 V * Forced fixed frequency * Internal compensation * Soft start * Enable/shutdown logic input * Overtemperature protection * Short-circuit protection * Reverse current capability * Undervoltage lockout protection * Small 10-lead 3 mm × 3 mm package, 1 mm height profile * Compact PCB footprint {{ :analog_discovery_2:ad2_33.png |Figure 32. 3.3V internal digital supply.}} //{{anchor:figure_32:Figure 32. 3.3V internal digital supply.}}// The main requirement for the 3.3V digital supply is the reverse current capability. When a user pin is overdriven the protection diode opens and back powers circuitry connected to this supply. If the back powered energy is higher than the used energy the regulator delivers it to its input, preventing the 3.3V from rising. The 1.8V digital power supply [[analog_discovery_2:refmanual#figure_33|(Fig. 33)]] is implemented with [[http://www.analog.com/en/power-management/switching-regulators-integrated-fet-switches/adp2138/products/product.html|ADP2138-1.8]] Fixed Output Voltage, 800mA, 3MHz, Step-Down DC-to-DC converter. This ensures a very small solution size due to the 3MHz switching frequency and the 1mm × 1.5 mm WLCSP package. The ADP2138 also features: * Input voltage: 2.3 V to 5.5 V * Peak efficiency: 95% * Typical quiescent current: 24 μA * Fast load and line transient response * 100% duty cycle low dropout mode * Internal synchronous rectifier, compensation, and soft start * Current overload and thermal shutdown protections * Ultra-low shutdown current: 0.2 μA (typical) * Forced PWM and automatic PWM/PSM modes {{ :analog_discovery_2:ad2_34.png |Figure 33. 1.8V internal digital supply.}} //{{anchor:figure_33:Figure 33. 1.8V internal digital supply.}}// ---- ===== 6.6. Temperature Measurement ===== The Analog Discovery 2 uses the [[http://www.analog.com/en/mems-sensors/digital-temperature-sensors/ad7415/products/product.html|AD7415]] Digital Output Temperature Sensor [[analog_discovery_2:refmanual#figure_2|(Fig. 34)]]. AD7415 main features are: * 10-bit temperature-to-digital converter * Temperature range: −40°C to +125°C * Typical accuracy of ±0.5°C at +40°C * SMBus/I2C®-compatible serial interface * Temperature conversion time: 29μs (typical) * Space-saving 5-lead SOT-23 package * Pin-selectable addressing via AS pin {{ :analog_discovery_2:figure_34.png |Figure 34. Temperature measurement.}} //{{anchor:figure_34:Figure 34. Temperature measurement.}}// ---- ===== 7. USB Controller ===== The USB interface performs two tasks: * **Programming the FPGA:** There is no non-volatile FPGA configuration memory on the Analog Discovery. The WaveForms software identifies the connected device and downloads an appropriate .bit file at power-up, via a Digilent USB-JTAG interface. Adept run-time is used for low level protocols. * **Data exchange:** All instrument configuration data, acquired data and status information is handled via a Digilent synchronous parallel bus and USB interface. Speed up to 20MB/sec. is reached, depending on USB port type and load as well as PC performance. ---- ===== 8. FPGA ===== The core of the Analog Discovery 2 is the Xilinx [[https://www.xilinx.com/products/silicon-devices/fpga/spartan-6.html|Spartan-6]] FPGA circuit XC6SLX16-1L. The configured logic performs: * Clock management (12 MHz and 60 MHz for USB communication, 100 MHz for data sampling) * Acquisition control and Data Storage (Scope and Logic Analyzer) * Analog Signal synthesis (look-up tables, AM/FM modulation for AWG) * Digital signal synthesis (for pattern generator) * Trigger system (trigger detection and distribution for all instruments ) * Power supplies control and instruments enabling * Power and temperature monitoring * Calibration memory control * Communication with the PC (settings, status data) Block and Distributed RAM of the FPGA are used for signal synthesis and acquisition. Multiple configuration files are available through the WaveForms software to allocate the RAM resources according to the application. Detail of the trigger system is shown in [[analog_discovery_2:refmanual#figure_35|Fig. 35]]. Each instrument generates a trigger signal when a trigger condition is met. Each trigger signal (including external triggers) can trigger any instrument and drive the external trigger outputs. This way, all the instruments can synchronize to each other. {{ :analog_discovery_2:figure_35.png |Figure 35. FPGA configuration trigger block diagram.}} //{{anchor:figure_35:Figure 35. FPGA configuration trigger block diagram.}}// ---- ===== 9. Features and Performances ===== This chapter shows the features and performances as described in the Analog Discovery 2 Datasheet. Footnotes add detailed information and annotate the HW description in this Manual. ===== 9.1. Analog Inputs (Scope) ===== * Channels: 2 * Channel type: differential((See note in section 2. Scope)) * Resolution: 14-bit * Absolute Resolution(scale ≤0.5V/div((High Gain: ±2.6V differential input voltage range.))): 0.32mV * Absolute Resolution(scale>0.5V/div((Low Gain: ±29V differential input voltage range.))): 3.58mV * Accuracy (scale≤0.5V/div, VinCM = 0V): ±10mV±0.5% * Accuracy (scale>0.5V/div, VinCM = 0V): ±100mV±0.5% * CMMR (typical): ±0.5% * Sample rate (real time): 100MS/s * Input impedance: 1MΩ||24pF * Scope scales: 500uV to 5V/div((High Gain or Low Gain is used in the analog signal input path for rough scaling. “Digital Zooming” is used for multiple scope scales.)) * Analog bandwidth with Discovery BNC adapter((The Scope bandwidth depends on probes. The Analog Discovery wire kit is an affordable, easy-to-use solution, but it limits the frequency, noise, and crosstalk performances (see [[analog_discovery_2:refmanual#figure_21|Figure 21]], down). With coax probes and Analog Discovery BNC adapter, the 0.5dB Scope bandwidth is 10 MHz (see Fig. 15).)): 30 MHz+ @ 3dB, 10 MHz @ 0.5dB, 5 MHz @ 0.1dB * Analog bandwidth with Wire Kit((The Scope bandwidth depends on probes. The Analog Discovery wire kit is an affordable, easy-to-use solution, but it limits the frequency, noise, and crosstalk performances (see [[analog_discovery_2:refmanual#figure_21|Figure 21]], down). With coax probes and Analog Discovery BNC adapter, the 0.5dB Scope bandwidth is 10 MHz (see Fig. 15).)): 9 MHz @ 3dB, 2.9 MHz @ 0.5dB, 0.8 MHz @ 0.1dB * Input range: ±25V (±50V diff((As shown in Fig. 12, a ±50V differential input signal does not fit in a single scope screen (ADC range). However, Vertical Position setting allows visualization of either +50V or -50V levels.))) * Input protected to: ±50V; * Buffer size/channel: Up to 16k samples((Default Scope buffer size is 8kSamples/channel. The WaveForms Device Manager provides alternate FPGA configuration files, with different resource allocation. With no memory allocated to the Digital I/O and reduced memory assigned to the AWG, the scope buffer size can be chosen to be 16kSamples/channel.)) * Triggering: edge, pulse, transition, hysteresis, etc.((Trigger Detectors and Trigger Distribution Networks are implemented in the FPGA. This allows real time triggering and cross-triggering of different instruments within the Analog Discovery device. Using external Trigger inputs/outputs, cross-triggering between multiple Analog Discovery devices is possible.)) * Cross-triggering with Logic Analyzer, Waveform Generator, Pattern Generator or external trigg((Trigger Detectors and Trigger Distribution Networks are implemented in the FPGA. This allows real time triggering and cross-triggering of different instruments within the Analog Discovery device. Using external Trigger inputs/outputs, cross-triggering between multiple Analog Discovery devices is possible.)). * Sampling modes: average, decimate, min/max((Real time sampling modes are implemented in the FPGA. The ADC always works at 100MS/s. When a lower sampling rate is required, (108/N samples/sec), N ADC samples are used to build a single recorded sample, either by averaging or decimating. In the Min/Max mode, every 2N samples are used to calculate and store a pair of Min/Max values. The stored sample rate is reduced by half in Min/Max mode.)) * Mixed signal visualization (analog and digital signals share same view pane)((In mixed signal mode, the scope and Digital I/O acquisition blocks use the same reference clock, for synchronization.)) * Real-time views: FFTs, XY plots, Histograms and other((This functionality is implemented by WaveForms software in the PC, using the buffered data from the FPGA. After a acquiring a complete data buffer at the FPGA level and uploading it to the PC, the data is processed and displayed, while a new acquisition is started.)) * Multiple math channels with complex functions. * Cursors with advanced data measurements((This functionality is implemented by WaveForms software in the PC, using the buffered data from the FPGA. After a acquiring a complete data buffer at the FPGA level and uploading it to the PC, the data is processed and displayed, while a new acquisition is started.)) * Captured data files can be exported in standard formats((This functionality is implemented by WaveForms software, in the PC.)) * Scope configurations can be saved, exported and imported((This functionality is implemented by WaveForms software, in the PC.)) ---- ===== 9.2. Analog Outputs (Arbitrary Waveform Generator) ===== * Channels: 2 * Channel type: single ended * Resolution: 14-bit * Absolute Resolution(amplitude ≤1V): 166μV * Absolute Resolution(amplitude >1V): 665μV * Accuracy - typical (|Vout| ≤ 1V): ±10mV ± 0.5% * Accuracy - typical (|Vout| > 1V): ±25mV ± 0.5% * Sample rate (real time): 100MS/s((The AWG DAC always works at 100MS/s. When a lower sampling rate is required, (108/N samples/sec), each sample is sent N times to the DAC.)) * AC amplitude (max): ±5 V((The AWG output voltage is limited to ±5V. This refers to the sum of AC signal and DC offset.)) * DC Offset (max): ±5 V((The AWG output voltage is limited to ±5V. This refers to the sum of AC signal and DC offset.)) * Analog bandwidth with Discovery BNC adapter((The AWG bandwidth depends on probes. The Analog Discovery wire kit is an affordable, easy-to-use solution, but it limits the frequency, noise, and crosstalk performances. With coax probes and Analog Discovery BNC adapter, the 0.5dB AWG bandwidth is 4MHz (see [[analog_discovery_2:refmanual#figure_21|Figure 21]]).)): 12 MHz @ 3dB, 4 MHz @ 0.5dB, 1 MHz @ 0.1dB * Analog bandwidth with Wire Kit((The AWG bandwidth depends on probes. The Analog Discovery wire kit is an affordable, easy-to-use solution, but it limits the frequency, noise, and crosstalk performances. With coax probes and Analog Discovery BNC adapter, the 0.5dB AWG bandwidth is 4MHz (see [[analog_discovery_2:refmanual#figure_21|Figure 21]]).)): 9 MHz @ 3dB, 2.9 MHz @ 0.5dB, 0.8 MHz @ 0.1dB * Slew rate (10V step): 400V/μs * Buffer size/channel: up to 16k samples((Default AWG buffer size is 4kSamples/channel. The WaveForms Device Manager provides alternate FPGA configuration files, with different resources allocation. With no memory allocated to the Digital I/O and reduced memory assigned to the Scope, the AWG buffer size can be 16kSamples/channel.)) * Standard waveforms: sine, triangle, sawtooth, etc. * Advanced waveforms: Sweeps, AM, FM((Real time implemented in the FPGA configuration.)). * User-defined arbitrary waveforms: defined within WaveForms software user interface or using standard tools (e.g. Excel)((This functionality is implemented by WaveForms software, in the PC.)). ---- ===== 9.3. Logic Analyzer ===== * Channels: 16 (shared)((All digital I/O pins are always available as inputs, to be acquired and displayed in the Logic Analyzer and Static I/O. The user selects which pins are also used as outputs, by the Pattern Generator or Static I/O. When a signal is driven by both Pattern Generator and Static I/O, the Static I/O has priority, except if Static I/O attempts to drive a HiZ value.)) * Sample rate (real time): 100MS/s * Buffer size/channel: up to 16K samples((Default Logic Analyzer buffer size is 4kSamples/channel. The WaveForms Device Manager provides alternate FPGA configuration files, with different resource allocation. With no memory allocated to the Scope and AWG, the Logic Analyzer buffer size can be chosen to be 16kSamples/channel.)) * Input logic: LVCMOS (1.8V/3.3V, 5V tolerant) * Multiple trigger options including pin change, bus pattern, etc((Trigger Detectors and Trigger Distribution Networks are implemented in the FPGA. This allows real time triggering and cross-triggering of different instruments within the Analog Discovery device. Using external Trigger inputs/outputs, cross-triggering between multiple Analog Discovery devices is possible.)). * Cross-triggering between Analog input channels, Logic Analyzer, Pattern Generator or external trigger((Trigger Detectors and Trigger Distribution Networks are implemented in the FPGA. This allows real time triggering and cross-triggering of different instruments within the Analog Discovery device. Using external Trigger inputs/outputs, cross-triggering between multiple Analog Discovery devices is possible.)). * Interpreter for SPI, I2C, UART, Parallel bus((This functionality is implemented by WaveForms software in the PC, using the buffered data from the FPGA. After a acquiring a complete data buffer at the FPGA level and uploading it to the PC, the data is processed and displayed, while a new acquisition is started.)). * Data file import/export using standard formats((This functionality is implemented by WaveForms software, in the PC.)). ---- ===== 9.4. Digital Pattern Generator ===== * Channels: 16 (shared)((All digital I/O pins are always available as inputs, to be acquired and displayed in the Logic Analyzer and Static I/O. The user selects which pins are also used as outputs, by the Pattern Generator or Static I/O. When a signal is driven by both Pattern Generator and Static I/O, the Static I/O has priority, except if Static I/O attempts to drive a HiZ value.)) * Sample rate (real time): 100MS/s * Algorithmic pattern generator (no buffers used)((Real time implemented in the FPGA configuration.)) * Custom pattern buffer/ch.: up to 16Ksamples((Default Pattern Generator buffer size is 1kSamples/channel. The WaveForms Device Manager provides alternate FPGA configuration files, with different resources allocation. With no memory allocated to the Scope and AWG, the Pattern Generator buffer size can be 16kSamples/channel.)) * Output logic standard: LVCMOS (3.3V, 12mA) * Data file import/export using standard formats((This functionality is implemented by WaveForms software, in the PC.)) * Customized visualization for signals and busses((This functionality is implemented by WaveForms software, in the PC.)). ---- ===== 9.5. Digital I/O ===== * Channels: 16 (shared)((All digital I/O pins are always available as inputs, to be acquired and displayed in the Logic Analyzer and Static I/O. The user selects which pins are also used as outputs, by the Pattern Generator or Static I/O. When a signal is driven by both Pattern Generator and Static I/O, the Static I/O has priority, except if Static I/O attempts to drive a HiZ value.)). * Input logic: LVCMOS (1.8V/3.3V, 5V tolerant) * Output logic standard: LVCMOS (3.3V, 4mA) * Virtual I/O devices (buttons, switches & displays)((This functionality is implemented by WaveForms software, in the PC.)). * Customized visualization options available((This functionality is implemented by WaveForms software, in the PC.)). ---- ===== 9.6. Power Supplies ===== * Voltage range: 0.5V…5V and -0.5V…-5V((WaveForms allows setting the user voltages in the range 0V…5V respectively -0V…-5V. However, voltages below 0.5V, respectively above -0.5V might have excessive ripple and should be used with caution.)). * Pmax (USB powered): 500mW total((This limit results from the overall device power balance: the power available from the USB port, minus the power internally used by the device, moderated by the user power supplies efficiency. The balance of 500mW is available for both user supplies to share.)) * Imax (USB powered): 700mA((This limit results from the structure of each user power supply (positive and negative). It is not conditioned by the load degree of the complementary user supply.)) for each supply * Pmax (AUX powered): 2.1W((This limit results from the structure of each user power supply (positive and negative). It is not conditioned by the load degree of the complementary user supply.)) for each supply * Imax (AUX powered): 700mA((This limit results from the structure of each user power supply (positive and negative). It is not conditioned by the load degree of the complementary user supply.)) for each supply * Accuracy (no load): ±10mV * Output impedance: 50mΩ (typical) ---- ===== 9.7. Network Analyzer*³ ===== * Shared instruments: Scope, AWG * Frequency sweep range: 1Hz to 10MHz * Frequency steps: 5 … 1000((This functionality is implemented by WaveForms software, in the PC.)). * Settable input amplitude and offset * Analog input records response at each frequency((This functionality is implemented by WaveForms software, in the PC.)). * Available diagrams: Bode, Nichols, or Nyquist((This functionality is implemented by WaveForms software, in the PC.)). ---- ===== 9.8. Voltmeters° ===== * Channels (shared with scope): 2 * Channel type: differential * Measurements: DC, AC, True RMS((This functionality is implemented by WaveForms software, in the PC.)). * Resolution: 14-bit * Accuracy (scale ≤0.5V/div): ±5mV * Accuracy (scale >0.5V/div): ±50mV * Input impedance: 1MΩ || 24pF * Input range: ±25V (±50V diff) * Input protected to: ±50V ---- ===== 9.9. Spectrum Analyzer°°===== * Channels (shared with scope): 2 * Power spectrum algorithms: FFT, CZT((This functionality is implemented by WaveForms software, in the PC.)). * Frequency range modes: center/span, start/stop((This functionality is implemented by WaveForms software, in the PC.)). * Frequency scales: linear, logarithmic((This functionality is implemented by WaveForms software, in the PC.)). * Vertical axis options: voltage-peak, voltage-RMS, dBV and dBu((This functionality is implemented by WaveForms software, in the PC.)). * Windowing: options: rectangular, triangular, hamming, Cosine, and many others((This functionality is implemented by WaveForms software, in the PC.)). * Cursors and automatic measurements: noise floor, SFDR, SNR, THD and many others((This functionality is implemented by WaveForms software, in the PC.)). * Data file import/export using standard formats((This functionality is implemented by WaveForms software, in the PC.)). ---- ===== 9.10. Other features ===== * USB power option; all needed cables included. * External supply option: 5V, 2.5A (not included) 5.5/2.1mm connector, positive inner pin * High-speed USB2 interface for fast data transfer * Waveform Generator output played on stereo audio jack * Trigger in/trigger out allows multiple instruments to be linked((Trigger Detectors and Trigger Distribution Networks are implemented in the FPGA. This allows real time triggering and cross-triggering of different instruments within the Analog Discovery device. Using external Trigger inputs/outputs, cross-triggering between multiple Analog Discovery devices is possible.)). * Cross triggering between instruments((Trigger Detectors and Trigger Distribution Networks are implemented in the FPGA. This allows real time triggering and cross-triggering of different instruments within the Analog Discovery device. Using external Trigger inputs/outputs, cross-triggering between multiple Analog Discovery devices is possible.)). * Help screens, including contextual help((This functionality is implemented by WaveForms software, in the PC.)). * Instruments and workspaces can be individually configured; configurations can be exported((This functionality is implemented by WaveForms software, in the PC.)). ---- *³The Network Analyzer instrument in WaveForms uses a channel of Analog Outputs (AWG) and all Analog Inputs (Scope) hardware resources. When it starts running, all other instruments using the same HW resources (competing instruments: AWG, Scope, Voltmeters, Spectrum Analyzer) are forced to a BUSY state. When running a competing instrument, the Network Analyzer is forced to a BUSY state °This instrument in WaveForms uses Analog Inputs (Scope) Hardware resources competing with other WaveForms instruments (Scope, Spectrum Analyzer, Network Analyzer, Voltmeter). When it starts running, the competing instruments are forced to a BUSY state. When running a competing instrument, this instrument is forced to a BUSY state. °°This instrument in WaveForms uses Analog Inputs (Scope) Hardware resources competing with other WaveForms instruments (Scope, Spectrum Analyzer, Network Analyzer, Voltmeter). When it starts running, the competing instruments are forced to a BUSY state. When running a competing instrument, this instrument is forced to a BUSY state. **Written by Mircea Dabacan, PhD, Technical University of Cluj-Napoca Romania**