====== JTAG-HS2 Reference Manual ====== The Joint Test Action Group (JTAG)-HS2 programming cable is a high-speed programming solution for Xilinx field-programmable gate arrays (FPGAs). The cable is fully compatible will all Xilinx tools and can be seamlessly driven from iMPACT, Chipscope, and EDK. The HS2 attaches to target boards using Digilent’s 6-pin, 100-mil spaced programming header or Xilinx’s 2x7, 2mm connector and the included adaptor. {{Digilent Image Gallery | image = {{reference/programmers/jtag-hs2/jtag-hs2-0.png?direct |}} | image = {{reference/programmers/jtag-hs2/jtag-hs2-1.png?direct |}} | image = {{reference/programmers/jtag-hs2/jtag-hs2-2.png?direct |}} | image = {{reference/programmers/jtag-hs2/jtag-hs2-3.png?direct |}} }} ==== Features ==== The PC powers the JTAG-HS2 through the USB port and will recognize it as a Digilent programming cable when connected to a PC, even if the cable is not attached to the target board. The HS2 has a separate Vdd pin to supply the JTAG signal buffers. The high speed 24mA three-state buffers allow target boards to drive the HS2 with signal voltages from 1.8V to 5V and bus speeds of up to 30MBit/sec. (See figure 1) To function correctly the HS2’s Vdd pin must be tied to the same voltage supply that drives the JTAG port on the FPGA. The JTAG bus can be shared with other devices as systems hold JTAG signals at high-impedance except when actively driven during programming. The HS2 comes included with a standard Type-A to Micro-USB cable that attaches to the end of the module opposite the system board connector. The system board connector should hold the small and light HS2 firmly in place. (See figure 2) * Small, complete, all-in-one JTAG programming solution for Xilinx FPGAs * Compatible with all Xilinx tools * Compatible with IEEE 1149.7-2009 Class T0 - Class T4 (includes 2-Wire JTAG) * Separate Vref drives JTAG/SPI signal voltages; Vref can be any voltage between 1.8V and 5V. * High-Speed USB2 port that can drive JTAG/SPI bus at up to 30Mbit/sec * JTAG/SPI frequency settable by user * Uses micro-AB USB2 connector * SPI programming solution (modes 0 and 2 up to 30Mbit/sec, modes 1 and 3 up to 2Mbit/sec) * Fully supported by the Adept SDK, allowing custom JTAG/SPI applications to be created {{ :programming_solutions:jtag_hs2:ove2.png?600 |}} {{ :programming_solutions:jtag_hs2:ove3.png?300|}} In addition to supporting JTAG, the JTAG-HS2 also features two highly configurable Serial Peripheral Interface (SPI) ports that allow communication with virtually any SPI peripheral. Both SPI ports share the same pins and only one port may be enabled at any given time. (See figure 3) The table in figure 4 summarizes the features supported by each port. The HS2 supports SPI modes 0, 1, 2, and 3. | __Figure 4__ |||||||| | **Port Number** | **SPI Mode** | **Shift LSB First** | **Shift MSB First** | **Selectable SCK Frequency** | **Max SCK Frequency** | **Min SCK Frequency** | **Inter-byte Delay** | | 0 | 0 | Yes | Yes | Yes | 30 MHz | 8 KHz | 0 – 1000 µS | | ::: | 2 | Yes | Yes | Yes | 30 MHz | 8 KHz | 0 – 1000 µS | | 1 | 0 | Yes | Yes | Yes | 2.066 MHz | 485 KHz | 0 – 1000 µS | | ::: | 1 | Yes | Yes | Yes | 2.066 MHz | 485 KHz | 0 – 1000 µS | | ::: | 2 | Yes | Yes | Yes | 2.066 MHz | 485 KHz | 0 – 1000 µS | | ::: | 3 | Yes | Yes | Yes | 2.066 MHz | 485 KHz | 0 – 1000 µS | ---- ===== Software Support ===== In addition to working seamlessly with all Xilinx tools, Digilent’s Adept software and the Adept software development kit (SDK) support the HS2 cable. For added convenience customers may freely downloaded the SDK from Digilent’s website. This Adept software includes a full-featured programming environment and a set of public application programming interfaces (API) that allow user applications to directly drive the JTAG chain. With the Adept SDK users can create custom applications that will drive JTAG ports on virtually any device. Users may utilize the API’s provided by the SDK to create applications that can drive any SPI device supporting those modes. Please see the Adept SDK reference manual for more information. ---- ===== IEEE 1149.7-2009 Compatibility ===== The JTAG-HS2 supports several scan formats including; the JScan0-JScan3, MScan, and OScan0 - OScan7. It is capable of communicating in 4-wire and 2-wire scan chains that consist of Class T0 – T4 JTAG Target Systems (TS). (See Figure 5 & 6) {{ :programming_solutions:jtag_hs2:ieee1.png?700 |}} //Figure 5// {{ :programming_solutions:jtag_hs2:ieee2.png?700 |}} //Figure 6// The Adept SDK provides an example application that demonstrates how to communicate with a Class T4 TAP controller using the MScan, OScan0, and OScan1 scan formats. ---- ===== Design Notes ===== The JTAG-HS2 uses high speed three-state buffers to drive the TMS, TDI, and TCK signals. These buffers are capable of sourcing or sinking a maximum of 50 mA of current. The HS2 has 100 ohm resistors between the output of the buffers and the I/O pins to ensure the cable does not exceed the maximum limit. To further limit short circuit current additional resistance may be placed in series with the I/O pins of the HS2 and the target board. However, Digilent recommends limiting the amount of additional resistance to 100 ohms or less as higher resistance may result in degraded operation. When the JTAG-HS2 first receives power the three-state buffers attached to the TMS, TDI, and TCK signals move into a high-impedance state. They remain in the high-impedance state until an application enables the HS2’s JTAG or SPI port. Once these ports activate, the buffers actively drive the TMS, TDI, and TCK signals until the port is disabled. The IEEE 1149.7-2009 specification requires any device that functions as a Debug and Test System (DTS) to provide a pull-up bias on the TMS and TDO pins. In order to meet this requirement, the JTAG-HS2 features weak pull-ups (100K ohm) on the TMS, TDI, TDO, and TCK signals. While not strictly required, the pull-ups on the TDI and TCK signals ensure that neither signal floats while another source is not actively driving them. {{ :programmers:jtag-hs2:jtag-input-output-stage.png?800 |}}