~~NOTOC~~ 
    
====== Nexys 3 ======
{{Digilent Infobox
| Manual = [[reference-manual]]
| Support = https://forum.digilent.com/forum/4-fpga/
| Title = Nexys 3
| Subtitle = Spartan-6 FPGA Trainer Board
| Header = Features
| Bullet = On-board USB2 port for programming & data transfer
| Header = Key Specifications
| Logic Cells =  2,278 slices (4 6-input LUTs \\ & 8 flip-flops each)
| Block RAM = 576Kbits
| Cellular RAM = 16Mbyte
| DSP Slices = 32
| Clock Tiles = 2 (4 DCMs & 2 PLLs)
| Internal clock = 500MHz+
| Oscillator = 100MHz CMOS
| Quad-SPI Flash = 16MB PCM non-volatile memory
| Ethernet = 10/100 PHY
| Header = Connectivity and On-board I/O
| USB = USB-UART and USB-HID port \\ (for mouse/keyboard)
| Pmod Connectors = 4
| VHDC = One connector
| VGA = 8-bit connector
| Display = 4-digit seven segment display
| Switches = 8
| Buttons = 5
| LEDs = 8
| I/O = 72 routed to expansion connectors
| Header = Electrical
| Power = USB \\ 5V (2.1mm coaxial) supply
| Logic Level = 3.3V
| Header = Physical
| Width = 4.8 in
| Length = 4.8 in
| Header = Design Resources
| Master UCF File = {{:reference:programmable-logic:nexys-3:nexys3_master_ucf.zip|}}
| EDK BSB Support Files = {{:reference:programmable-logic:nexys-3:nexys3_bsb_support_v_2_8.zip|}}
| Board Verification = {{:reference:programmable-logic:nexys-3:nexys3_factory_config.zip|ZIP}}
| Header = Documentation
| Primary IC = [[https://www.xilinx.com/products/silicon-devices/fpga/spartan-6.html | Spartan-6]] (XC6LX16-CS324)
| Reference Manual = [[programmable-logic/nexys-3/reference-manual]]
| Schematic = {{:reference:programmable-logic:nexys-3:nexys3_sch.pdf|Rev. B}}
}}

{{page>reference-manual}} \\ \\
 
===== Tutorials =====
{{topic>nexys-3 +tutorial}}

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===== Example Projects =====
{{topic>nexys-3 +project}}

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===== Additional Resources =====
== Demonstration projects ==
  * **VmodTFT Project** -- {{:nexys:nexys3:vmodtft_simple_paint_demo.zip|ZIP}}
    * This demo project is for the VmodTFT and either the Nexys3 or the Atlys. It continuously samples the VmodTFT's touch panel for X, Y and pressure values and lights up the pixels touched.

== Pmod Projects - Verilog ==

  * **PmodACL** -- {{:nexys:nexys3:pmodacl_demo_verilog.zip|ZIP}}
    * This zip file contains a Xilinx ISE demo project for the PmodACL. 
    * This project was made for Xilinx ISE 14.2, targets the Nexys 3, and is written in Verilog.
  * **PmodCLP** -- {{:nexys:nexys3:pmodclp_demo_verilog.zip|ZIP}}
    * This zip file contains a Xilinx ISE demo project for the PmodCLP. 
    * This project was made for Xilinx ISE 14.2, targets the Nexys 3, and is written in Verilog. 
  * **PmodCLS** -- {{:nexys:nexys3:pmodcls_demo_verilog.zip|ZIP}}
    * This zip file contains a Xilinx ISE demo project for the PmodACL. 
    * This project was made for Xilinx ISE 14.2, targets the Nexys 3, and is written in Verilog.
  * **PmodENC** -- {{:nexys:nexys3:pmodenc_demo_verilog.zip|ZIP}}
    * This zip file contains a Xilinx ISE demo project for the PmodENC. 
    * This project was made for Xilinx ISE 14.2, targets the Nexys 3, and is written in Verilog.
  * **PmodGYRO** -- {{:nexys:nexys3:pmodgyro_demo_verilog.zip|ZIP}}
    * This zip file contains a Xilinx ISE demo project for the PmodGYRO. 
    * This project was made for Xilinx ISE 14.2, targets the Nexys 3, and is written in Verilog.
  * **PmodHB5** -- {{:nexys:nexys3:pmodhb5_demo_verilog.zip|ZIP}}
    * This zip file contains a Xilinx ISE demo project for the PmodHB5. 
    * This project was made for Xilinx ISE 14.2, targets the Nexys 3, and is written in Verilog.
  * **PmodJSTK** -- {{:nexys:nexys3:pmodjstk_demo_verilog.zip|ZIP}}
    * This zip file contains a Xilinx ISE demo project for the PmodJSTK. 
    * This project was made for Xilinx ISE 14.2, targets the Nexys 3, and is written in Verilog.
  * **PmodKYPD** -- {{:nexys:nexys3:pmodkypd_demo_verilog.zip|ZIP}}
    * This zip file contains a Xilinx ISE demo project for the PmodKYPD. 
    * This project was made for Xilinx ISE 14.2, targets the Nexys 3, and is written in Verilog.
  * **PmodOLED** -- {{:nexys:nexys3:pmodoledctrl_verilog.zip|ZIP}}
    * This zip file contains a Xilinx ISE demo project for the PmodOLED. 
    * This project was made for Xilinx ISE 14.2, targets the Nexys 3, and is written in Verilog.
  * **PmodPS2** -- {{:nexys:nexys3:pmodps2_demo_verilog.zip|ZIP}}
    * This zip file contains a Xilinx ISE demo project for the PmodPS2. 
    * This project was made for Xilinx ISE 14.2, targets the Nexys 3, and is written in Verilog.

== Pmod Projects - VHDL ==
  * **PmodACL** -- {{:nexys:nexys3:pmodacl_demo.zip|ZIP}}
    * This zip file contains a Xilinx ISE demo project for the PmodACL. 
    * This project was made for Xilinx ISE 14.2, targets the Nexys 3, and is written in VHDL.
  * **PmodCLP** -- {{:nexys:nexys3:pmodclp_demo.zip|ZIP}}
    * This zip file contains a Xilinx ISE demo project for the PmodCLP. 
    * This project was made for Xilinx ISE 14.2, targets the Nexys 3, and is written in VHDL. 
  * **PmodCLS** -- {{:nexys:nexys3:pmodcls_demo.zip|ZIP}}
    * This zip file contains a Xilinx ISE demo project for the PmodACL. 
    * This project was made for Xilinx ISE 14.2, targets the Nexys 3, and is written in VHDL.
  * **PmodENC** -- {{:nexys:nexys3:pmodenc_ise_demo.zip|ZIP}}
    * This zip file contains a Xilinx ISE demo project for the PmodENC. 
    * This project was made for Xilinx ISE 14.2, targets the Nexys 3, and is written in VHDL.
  * **PmodGYRO** -- {{:nexys:nexys3:pmodgyro_demo.zip|ZIP}}
    * This zip file contains a Xilinx ISE demo project for the PmodGYRO. 
    * This project was made for Xilinx ISE 14.2, targets the Nexys 3, and is written in VHDL.
  * **PmodHB5** -- {{:nexys:nexys3:pmodhb5_demo_project.zip|ZIP}}
    * This zip file contains a Xilinx ISE demo project for the PmodHB5. 
    * This project was made for Xilinx ISE 14.2, targets the Nexys 3, and is written in VHDL.
  * **PmodJSTK** -- {{:nexys:nexys3:pmodjstk_demo.zip|ZIP}}
    * This zip file contains a Xilinx ISE demo project for the PmodJSTK. 
    * This project was made for Xilinx ISE 14.2, targets the Nexys 3, and is written in VHDL.
  * **PmodKYPD** -- {{:nexys:nexys3:pmodkypd_demo.zip|ZIP}}
    * This zip file contains a Xilinx ISE demo project for the PmodKYPD. 
    * This project was made for Xilinx ISE 14.2, targets the Nexys 3, and is written in VHDL.
  * **PmodOLED** -- {{:nexys:nexys3:pmodoledctrl.zip|ZIP}}
    * This zip file contains a Xilinx ISE demo project for the PmodOLED. 
    * This project was made for Xilinx ISE 14.2, targets the Nexys 3, and is written in VHDL.
  * **PmodPS2** -- {{:nexys:nexys3:pmodps2_demo.zip|ZIP}}
    * This zip file contains a Xilinx ISE demo project for the PmodPS2. 
    * This project was made for Xilinx ISE 14.2, targets the Nexys 3, and is written in VHDL.

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{{tag>legacy programmable-logic programmable-logic-start nexys-3 resource-center}}