~~TechArticle~~
====== Getting Started with Vivado and Vitis for Baremetal Software Projects ======

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===== Overview =====
This guide will work you through the process of setting up a project in Vivado and Vitis. A simple hardware design including a processor with several AXI GPIO peripherals connected to buttons and LEDs will be created. This design will then be exported to the Vitis IDE, and a baremetal software project will be created and run which polls the buttons and writes to the LEDs.

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===== Requirements =====
  * A Digilent FPGA Development Board
    * USB Programming cables, USB UART cables, and Power Supply, as required by the board.
    * **Note:** //The Genesys ZU is not supported by this guide, as it uses a Zynq Ultrascale+ MPSoC part, and requires additional configuration of its bootloader. Please see the getting started info specific to it, found on its [[programmable-logic/genesys-zu/start|Resource Center]].//
  * Vivado and Vitis installations
    * See [[programmable-logic:guides:installing-vivado-and-vitis]] for instructions on how to install these tools.
    * You also need the board files for your board. This guide is intended for use with the board files available from Digilent's vivado-library repo on Github. You can get these files using the process described in the [[installing-vivado-and-vitis]] guide. 

<WRAP round info>
Screenshots presented in this guide may not have been taken with your version of the tools. The workflow process presented here has been verified in Vivado and Vitis 2022.1.

Substantial UI changes in Vitis 2023.2 have changed much of the specifics of how to create a project in that tool. For a detailed rundown of changes, check out Adam Taylor's post about it on the [[https://www.adiuvoengineering.com/post/microzed-chronicles-introducing-vitis-unified-ide|adiuvoengineering blog]]. Note that the source code provided in this tutorial may also not work with versions 2023.2 or newer.

If you are using a version of Vivado that includes Xilinx SDK (2019.1 or older), check out [[vivado/getting-started-with-ipi/2018.2]] instead.
</WRAP>

<WRAP round info>
The user Viktor Nikolov posted a tutorial on the Digilent Forum with an alternate architecture for clocking the DDR interface for Digilent boards that use MicroBlaze - namely the Arty A7, Arty S7, Nexys A7, Nexys Video, and USB104 A7. It works around several errors that may occur in the flow presented here and is recommended for new users to go through. Digilent is considering updating this and other guides and reference material to use the revised flow. Find more information and a comprehensive guide here: [[https://forum.digilent.com/topic/27389-arty-a7-microblaze-ddr3-tutorial/]].
</WRAP>

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===== Guide =====

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It's time to program your Digilent board! Plug it into your computer through its USB programming and USB UART port/s, connect an external power supply (if necessary), and turn on the board.
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{{page>programmable-logic:guides:vitis-launch-app&showheader}}

==== Next Steps ====

At this point, your application is running, and printed messages can be seen. Congratulations, you have finished this guide!!!

The hardware project and application created here can be used as a basis for future work. See instructions found in [[programmable-logic:guides:vitis-update-hardware-specification]] for additional information on how the hardware design can be switched out later.

For more guides and demos for your board, return to the device's resource center, linked from the [[programmable-logic:start|Programmable Logic]] page of this wiki.

For technical support, please visit the [[https://forum.digilent.com/forum/4-fpga/|FPGA]] section of the Digilent Forums.