~~NOTOC~~ 
      
====== Atlys ======
{{Digilent Infobox
| Manual = [[reference-manual]]
| Support = https://forum.digilent.com/forum/4-fpga/
| Title = Atlys
| Subtitle = Spartan-6 FPGA Trainer Board 
| Header = Key Specifications
| Logic Cells = 6,822 slices
| Block RAM = 2.1Mbits
| Clock Tiles = 4 (8 DCMs & 4 PLLs)
| PLLs = 6
| DDR2 = 128MB with 16-bit wide data
| DSP Slices = 58
| Internal clock = 500MHz+
| Oscillator = 100MHz CMOS
| Quad-SPI Flash = 16MB
| Ethernet = 10/100/1000 PHY
| Header = Connectivity and Onboard I/O
| Pmod Connectors = 4
| USB = 2 on-board USB2 ports for \\ programming and data transfer
| HDMI = 2 HDMI input and output ports
| Audio = AC-97 Codec with line-in, \\ line-out, mic, and headphone
| IOs = 48 I/Os routed to expansion \\ connectors
| Pmod Connectors = 1 12-pin Pmod port
| Vmod Connectors = 1 Vmod (high-speed VHDC) \\ connector
| Switches = 8 slide switches
| Buttons = 6
| LEDs = 8
| Header = Electrical
| Power = 5V (2.1mm) supply
| Logic Level = 3.3v
| Header = Physical
| Width = 4.8 in
| Length = 5.3 in
| Header = Design Resources
| Master UCF = {{:reference:programmable-logic:atlys:atlysgeneralucf.zip|ZIP}}
| Atlys Support Files = {{:reference:programmable-logic:atlys:atlys_bsb_support_v_3_7.zip|ZIP}}
| Header = Documentation
| Primary IC = [[https://docs.xilinx.com/v/u/en-US/ds160|Spartan-6 LX45]] \\ (XC6SLX45-CSG324C)
| VHDCI Plug = {{atlys/atlys/r-hi-008068-2_plug.pdf|Datasheet}}
| VHDCI Receptacle = {{atlys/atlys/r-hs-008068-2c_receptacle.pdf|Datasheet}}
| Reference Manual = [[programmable-logic/atlys/reference-manual]]
| Schematic = {{:reference:programmable-logic:atlys:atlys_sch.pdf|Rev. C}}
}}

{{page>reference-manual}} \\ \\
 
===== Tutorials =====
{{topic>atlys +tutorial}}

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===== Example Projects =====
{{topic>atlys +project}}

  * **Atlys Demo/BIST Config** -- {{:atlys:atlys:atlys_demo_bist_clean.zip|ZIP}} 
    * Source code for Atlys Demo/BIST configuration (factory loaded into SPI Flash)
  * **Flash Memory Config** -- {{:atlys:atlys:atlys_mantest3_initmemtest_clean.zip|ZIP}} 
    * Source code for Atlys DDR2 and SPI Flash memory controller configuration
  * **VmodTFT Demo** -- {{:atlys:atlys:vmodtft_simple_paint_demo.zip|ZIP}} 
    * This demo project is for the VmodTFT and either the Nexys3 or the Atlys. It continuously samples the VmodTFT's touch panel for X, Y and pressure values and lights up the pixels touched.
  * **EDK Microblaze Demo** -- {{:atlys:atlys:atlys_ac97_edk_demo.zip|Download}} 
    * This zip file contains an EDK demo project that illustrates how to use the AC97 codec on the Atlys board with Microblaze.
  * **EDK HDMI Demo** -- {{:atlys:atlys:atlys_hdmi_plb_demo.zip|ZIP}} 
    * This zip file contains an EDK demo project that demonstrates using HDMI on the Atlys board. It accepts an HDMI input, buffers the input frames into memory, and then outputs the buffer to another HDMI port. This is implemented using PLB bus.
  * **ISE Demo** -- {{:atlys:atlys:atlys_ise_gpio_uart.zip|ZIP}}
  * {{:atlys:atlys:atlys_ise_gpio_uart.zip|Download}} This zip file contains an ISE demo project that demonstrates the use of general I/O and UART on the Atlys board in VHDL.
  * **EDK Web Server** -- {{:atlys:atlys:atlys_axi_web_server_demo_v_1_02.zip|ZIP}} 
    * This zip file contains an EDK demo project that illustrates how to host a web server on the Atlys. It was built using EDK 14.3.



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===== Additional Resources =====

===== Firmware =====

  * **Binary Image for BIST** --  {{:atlys:atlys:atlys4.zip|ZIP}} 
    * Built binary image for Atlys_Demo_BIST. This can be used to restore the original factory image in the Atlys SPI Flash. To reprogram, use the Flash tab in the Adept Application.

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{{tag>legacy programmable-logic programmable-logic-start atlys resource-center}}