====== Nexys Video - Getting Started with Microblaze Servers ======
{{ :nexys:nexysvideo:16508527298_efc2312db1_o_1_.png?direct&500 |}}

**Note:**The Nexys Video uses a Gigabit Ethernet module which requires the TEMAC IP that is **not contained in the Vivado Webpack**. In order to complete this tutorial, you must either purchase a license for the TEMAC IP or get the evaluation license for free from their website by following [[vivado:temac|this guide]].

===== Overview =====
This guide will provide a step by step walk-through of creating a Microblaze based hardware design using the Vivado IP Integrator that will build over the [[learn/programmable-logic/tutorials/nexys-video-getting-started-with-microblaze/start|Getting Started with Microblaze]] guide by making use of the on-board Ethernet port and GPIOs for the Nexys Video FPGA board. 

At the end of this tutorial you will have a comprehensive hardware design for Nexys Video that makes use of various Hardware ports on the Nexys Video which are managed by the Microblaze Softcore Processor block.

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===== Prerequisites =====

=== Skills ===
  * **Familiarity with Vivado**
    * This experience can be found by walking through our "Getting Started with Vivado" guide.

=== Hardware ===
  * **Nexys Video FPGA Board**
  * **2 Micro USB Cables**
    *  For UART communication and JTAG programming.
  * **Ethernet Cable**

=== Software ===
  * **Xilinx Vivado with the SDK package.** 
    * Follow this Wiki guide: [[vivado:installation|Installing Vivado]] on how to install and activate Vivado.
  * **TEMAC IP license installed**
    * Follow this Wiki guide: [[vivado:temac|Installing the 120 Day Evaluation License for the TEMAC IP]].

=== Board Support Files ===
  * **Nexys Video Support Files** 
    * These files will describe GPIO interfaces on your board and make it easier to select your FPGA board and add GPIO IP blocks.
    * Follow this Wiki guide ([[vivado:boardfiles|Vivado Board Files for Digilent 7-Series FPGA Boards]]) on how to install Board Support Files for Vivado.

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===== Tutorial =====
Microblaze is a soft IP core from Xilinx that will implement a microprocessor entirely within the Xilinx FPGA general purpose memory and logic fabric. For this tutorial, we are going to add Ethernet functionality and create an echo server.

=== General Design Flow ===

I. Vivado 
  * Open Vivado and select Nexys Video board
  * Create an new Vivado Project
  * Create empty block design workspace inside the new project
  * Add required IP blocks using the IP integrator tool and build Hardware Design
  * Validate and save block design
  * Create HDL system wrapper
  * Run design Synthesis and Implementation 
  * Generate Bit File
  * Export Hardware Design including the generated bit stream file to SDK tool
  * Launch SDK

Now the Hardware design is exported to the SDK tool. The Vivado to SDK hand-off is done internally through Vivado.
We will use SDK to create a Software application that will use the customized board interface data and FPGA hardware configuration by importing the hardware design information from Vivado.

II. SDK
  * Create new application project and select default Hello World template
  * Program FPGA
  * Run configuration by selecting the correct UART COM Port and Baud Rate
==== 1. Creating a New Project ====

>1.1) Open up Vivado and click **Create New Project** to open Vivado's New Project wizard.
>
>{{:basys3:basys3_screen_shot_2015-6-10_1.png?direct&500|}}

>1.2)  A new window will open up, click **Next** and you'll see the screen below. Name your project (no spaces!) and choose your project saving directory before clicking **Next**. Underscores are a good substitute for empty spaces.
>
>{{:basys3:basys3_screen_shot_2015-6-10_2.png?direct&500|}}

>1.3) We will be building this project from the ground up and adding our own sources so we will want to create an RTL project. Select RTL Project and leave the **Do not specify sources** box unchecked. Click **Next**.
>
>{{:basys3:basys3_screen_shot_2015-6-10_3.png?direct&500|}}

>1.4) If you have followed the Board Support File Wiki guide then click **Next** and select **Boards**. From the filter options make required selections for Vendor, Display Name and Board Revision. **Nexys Video** should be displayed in the selection list. A mismatch in selecting the correct board name will cause errors. 
>
>{{:nexys:nexysvideo:2.jpg?direct&500|}}

>1.5) Click **Next**, a summary of the new project design sources and target device is displayed. Click **Finish**.
>
>{{:vivado:mig_3.jpg?direct&500|}}

At this point you have successfully created a project that will properly communicate with the Nexys Video.

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==== 2. Creating the Block Design ====

>2.1) This is the main project window where you can create a IP based block design or add RTL based design sources.  The flow navigator panel on the left provides multiple options on how to create a hardware design, perform simulation, run synthesis and implementation and generate a bit file. You can also program the board directly from Vivado with the generated bit file for an RTL project using the Hardware Manager.
>
>For our design, we will use the IP Integrator to create a new block design.
>
>{{:vivado:mig_4.jpg?direct&500|}}

>2.2) On the left you should see the Flow Navigator. Select **Create Block Design** under the IP Integrator. Give a name to your design without any spaces.
>
>{{:vivado:mig_5.jpg?direct&500|}}

=== Add the Microblaze Core: ===
>2.3) An empty design workspace is created where you can add IP blocks. You can click on the //"Add IP"// message prompt on the top or click on the {{:genesys2:addip.jpg?nolink|}} **Add IP** button. This should open a catalog of pre-built IP blocks from Xilinx IP repository. Search for //"Microblaze"// and double click on it to add the IP block to your empty design. 
>
>{{:vivado:mig_6.jpg?direct&500|}}

>2.4) This is the Xilinx Microblaze IP block. When a new IP block is added the user can customize the block properties by either clicking on the //"Run Block Automation"// message prompt or by double clicking on the block itself.
>
>{{:vivado:mig_7.jpg?direct&500|}}

>2.5) Run Block Automation and a customization assistant window will open with default settings.
>
>{{:vivado:mig_8.jpg?direct&500|}}

>2.6) Change default settings in the block options as shown below and click **OK**. This will customize the block with our new user settings. **Do not click on Run Connection Automation yet.**
>
>{{:nexys:nexysvideo:4.jpg?direct&500|}}

=== Adding the Necessary Output Clocks: ===

>2.7) Double click the Clocking Wizard (clk_wiz_1) block highlighted below, and set CLK_IN1 to use "sys_clock" and EXT_RESET_IN to use "reset".
>
>{{:nexys4-ddr:server_4.jpg?direct&500|}}

>2.8) Select the Output Clocks tab and enable //clk_out2//, //clk_out3//. Set //clk_out2// to **200MHz**, and //clk_out3// to **125MHz**. Set the Reset Type to **Active Low**. When you are finished, click **OK**.
>
>{{:nexys:nexysvideo:6.jpg?direct&500|}}

=== Adding More Interrupts: ===

>2.9) Find the //Concat// block and double click it. Set number of ports to 5 and press **OK**.
>
>{{:nexys:nexysvideo:5.jpg?direct&500|}}

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==== 3. Adding the IP Cores ====

>3.1) We will now add all of the necessary IP blocks to our project. There are 4 cores we will add:
   - Memory Interface Generator
   - AXI Uartlite
   - AXI Ethernet Subsystem
   - AXI Timer


>3.2) Add all of these to your design, one at a time, using the {{:genesys2:addip.jpg?nolink|}} **Add IP** button button. Once they are all added, you should see the four blocks shown below.
>
>{{:nexys:nexysvideo:7.jpg?direct&500|}}

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==== 4. Configuring and Routing the IP Cores ====

>4.1) Click **Run Block Automation** and run it for the **mig_7series_0** block.
>
>{{:nexys:nexysvideo:8.jpg?direct&500|}}
>
>When the MIG block automation is run, you will see this specific error message [BD 41-1273]. You can ignore this for now. It will not affect your design in any way. The MIG block will be configured as per the board support files that have been downloaded for Nexys Video. Click **OK** to dismiss this message. You will find the MIG IP block now has additional input and output pins which have to be connected to valid signals.
>
>{{:nexys4-ddr:mig_27-2.jpg?direct&500|}}

>4.2) Click //"Run Block Automation"// and run it for the **axi_ethernet_0** block. Change //Physical Interface Selection// to **RGMII** and click **OK**.
>
>{{:nexys:nexysvideo:9.jpg?direct&500|}}

>4.3) Click //"Run Connection Automation"//. Un-check the **microblaze_0** check-box and click **OK**.
>
>{{:nexys:nexysvideo:10.jpg?direct&500|}}

>4.4) Click //"Run Connection Automation"// again. Run this for the **axi_ethernet_0_dma**.
>
>{{:nexys:nexysvideo:11.jpg?direct&500|}}

>4.5) Click //Regenerate Layout// (circled in blue below), and your block design should look like this:
>
>{{:nexys:nexysvideo:12.jpg?direct&500|}}

=== Routing the Missing Connections ===

>4.6) The //Concat// block takes interrupt inputs and sends them to the Microblaze controller.
>
>{{:nexys:nexysvideo:concat.jpg?direct&300|}}
>
>Route the following connections to the inputs of the //Concat// block; order does not matter:
>   - **interrupt** on the //AXI Timer// block.
>   - **mm2s_introut** and **s2mm_introut** on the //axi_ethernet_0_dma// block.
>   - **mac_irq** and **interrupt** on the //axi_ethernet_0// block.
>
>{{:nexys:nexysvideo:13.jpg?direct&500|}}

>4.7) Connect **resetn** on the //Clocking Wizard// block to the **reset** pin input.
>
>{{:nexys4-ddr:server_14.jpg?direct&500|}}

>4.8) Connect **sys_clk_i** on the //mig_7_series_0// block to the **clk_out2** output from the //Clocking Wizard//.
>
>{{:nexys:nexysvideo:14.jpg?direct&500|}}

>4.9) Right click on the blue striped rectangle next to the **DDR3+** bus on the //Memory Interface Generator// block and click **Make External**.
>
>{{:arty:9.jpg?direct&500|}}

>4.10) Clicking //Regenerate Layout// again will result in your final block design layout for this project.
>
>{{:nexys:nexysvideo:15.jpg?direct&500|}}

>4.11) Click the **Validate Design** {{:nexys:nexysvideo:validate.jpg?nolink|}} button to make sure that you did not make any errors.

>4.12) Now, right click on your design_1 block diagram and click **Create HDL Wrapper**. When the window pops up, select the **Let Vivado manage wrapper and auto-update** bullet and click **OK**.
>
>{{:nexys4-ddr:server_22.jpg?direct&500|}}

>4.13) Click **Generate Bitstream** at the top of the work space. This process will take a while.
>
>{{:nexys4-ddr:server_23.jpg?direct&500|}}

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==== 5. Exporting Hardware Design to SDK ====

>5.1) On the top left corner of the window, from the tool bar click on //File// and select //Export Hardware//.
>This will export the hardware design with system wrapper for the Software Development Tool - Vivado SDK. 
>**Make sure the generated bitstream is included by checking the box**.
>
>{{:nexys4-ddr:server_24.jpg?direct&500|}}

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==== 6. Launching SDK ====

>6.1) Go to //File// and select //Launch SDK// and click OK. The SDK file created local to the Vivado design project location will be launched. The hand-off to SDK from Vivado is complete. 
>
>{{:vivado:mig_45.jpg?direct&500|}}

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==== 7. Inside SDK for Vivado ====

>7.1) A new window for SDK will open. The HW design specification and included IP blocks are displayed in the //system.hdf// file. SDK tool is independent of Vivado, i.e. from this point, you can create your SW project in C/C++ on top of the exported HW design. If necessary, you can also launch SDK directly from the SDK folder created in the main Vivado Project directory. 
>
>Now, if you need to go back to Vivado and make changes to the HW design, then it is recommended to close the SDK window and make the required HW design edits in Vivado. After this you must follow the sequence of creating a new HDL wrapper, save design and bit file generation. This new bit file and system wrapper must then be exported to SDK. 
>
>Since we do not have any HW design edits at this point, we will proceed with creating a software application to run an echo server.
>
>{{:vivado:mig_46.jpg?direct&500|}}

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==== 8. Creating New Application Project in SDK ====

>8.1) Go to //File// in the main tool bar and select **New->Application Project**. A new project window will pop up. Give your SDK project a name that has no empty spaces as shown below. Make sure the //Target Hardware// is the correct hardware design. In our case, it will be **design_1_wrapper_hw_platform_0**. 
>
>If for example, you also have another hardware design in the //Project Explorer// window, then you will also see this design name in the Target Hardware drop down selection list. 
>
>Since we only have one hardware design  **design_1_wrapper_hw_platform_0** this will be our target hardware.  Select **Create New** under **Board Support Package**. The tool will automatically populate the **Board Support Package** name to match with the give project name. Click **Next**.
>
>{{:nexys4-ddr:server_25.jpg?direct&500|}}

>8.2) Select //IwIP Echo Server// under the list of available templates and click **Finish**.
>
>{{:nexys4-ddr:server_26.jpg?direct&500|}}

After completing the previous step, you will see two new folders in the //Project Explorer// panel. **echo_server** which contains all the binaries, .C and .H (Header) files, and **echo_server_bsp** which is the board support folder.

**echo_server** is our main working source folder. This also contains an important file shown here in the src folder called //lscript.ld//. This is a Xilinx auto generated linker script file. Double click on this file to open.

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==== 9. Verify Linker Script File for Memory Region Mapping ====

>9.1) In the linker script, take a look at the **Section to Memory Region Mapping** box. If you did the //Make DDR3 External// step then the target memory region **must** read **mig_7series_0**. 

>9.2) Scroll down to check if this applies to all rows.  If for any region it does not say **mig_7series_0**, then click on the row under the **Memory Region** column and select **mig_7series_0**.
>
>{{:nexys4-ddr:server_28.jpg?direct&500|}}

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==== 10. Setting PHY Link Speed ====

>10.1) Open the //system.mss// file within the //echo_server_bsp// folder and click **Modify this BSP's Settings**. 
>
>{{:nexys4-ddr:server_30.jpg?direct&500|}} 

>10.2) Once in **Board Support Package Settings** select **Overview -> standalone -> lwip141**. The configuration table for the lwip141 library should now be visible on the right. Navigate to **temac_adapter_options -> phy_link_speed**. Here you will need to change **CONFIG_LINKSPEED_AUTODETECT** to **CONFIG_LINKSPEED100** so that it looks like the picture below.
>
>{{:arty:server_31.png?direct&500|}}

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==== 11. Programming FPGA with Bit File ====

>11.1) Make sure that the board is turned on and connected to the host PC with the provided micro USB cable. On the main toolbar, click **Xilinx Tools -> Program FPGA** 
>Make sure that the //Hardware Platform// is selected as **design_1_wrapper_hw_platform_0**. 
>
>In the software configuration box, under //ELF File to Initialize in Block RAM// column, the row option must read **bootloop**. If not, click on the row and select **bootloop**.
>
>Now click on **Program**. 
>
>{{:nexys4-ddr:server_29.jpg?direct&500|}}

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==== 12. Setting up the SDK Serial Console and Running the Server ====

>12.1) Make sure both the UART and the JTAG USB ports are plugged into your Nexys Video. Right click on the //echo_server// project folder and select **Run As -> Run Configurations**
>
>{{:nexys4-ddr:server_32.jpg?direct&500|}}

>12.2) Go to the //STDIO Connection// tab and check the //Connect STDIO to Console// check-box. Click **Apply**, then click **Run**.
>
>{{:nexys4-ddr:server_33.jpg?direct&500|}}

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==== 13. Running the Server ====

>13.1) In the console window at the bottom of the screen the details of the connection will be displayed.
>
>{{:learn:programmable-logic:tutorials:nexys-video-getting-started-with-microblaze-servers:server.jpg?direct&600|}}

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==== 14. Testing the Server with Tera Term ====

>14.1) Connect your PC to your board using an Ethernet cable. **If using a router, watch the UART console to find out the IP of the Nexys Video echo server, and connect to that IP address. Setting up the connection as static is unnecessary.**

>14.2) In order to connect to the echo server directly from your computer, you must set up your Ethernet connection with a static IP address. To do this:
>
>
>>14.2.1) Right click your internet connection and click **Open Network and Sharing Center**.
>>
>>{{:nexys4-ddr:server_35.jpg?direct&500|}}
>
>>14.2.2) Find the Ethernet Connection to your board. It should be an unidentified network. Click **Local Area Connection**.
>>
>>{{:nexys4-ddr:server_36.jpg?direct&500|}}
>
>>14.2.3) Click **Properties**. 
>>
>>{{:nexys4-ddr:server_37.jpg?direct&500|}}
>
>>14.2.4) Select **Internet Protocol Version 4 (TCP/IPv4)** and click **Properties**.
>>
>>{{:nexys4-ddr:server_38.jpg?direct&500|}}
>
>>14.2.5) Click the **Use the following IP address:** bullet and type in an IP address "192.168.1.XX", where XX is a value between 2 and 255, but not 10. **This IP must not be the same as another already on your network**. Make sure to click within the //Subnet mask// field to get the 255.255.255.0 mask to autofill. Click **Ok** and you will have a static IP address.
>>
>>{{:nexys4-ddr:server_39.jpg?direct&500|}}

>14.3) Open Tera Term and type in the following info and click **Ok**.
>
>{{:nexys-video:server_40.jpg?direct&500|}}

>14.4) Type anything into the console and press Enter. The echo server will echo back your input and display it in the console.
>
>//You can go to Setup->Terminal and change the settings below for a more traditional echo server format//
>
>{{:nexys4-ddr:11.jpg?direct&500|}}

{{tag>learn programmable-logic tutorial nexys-video microblaze}}