====== Nexys 4 DDR XADC Demo ======

{{:nexys:nexys4:xadc6.jpg?500|}}

===== Overview =====
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The Nexys 4 DDR was rebranded as the Nexys A7 starting with Revision D starting in 2018. Updated releases of this particular demo project, usable by all versions of both the Nexys 4 DDR and the Nexys A7 can be found in the [[/programmable-logic/nexys-a7/start#example_projects|Nexys A7 Resource center]].
</WRAP>

==== Description ====

This simple XADC Demo project demonstrates a simple usage of the Nexys-4DDR's 
XADC port capability. The behavior is as follows:
 
  * The 16 User LEDs increment from right to left as the voltage difference on the selected XADC pins gets larger.
  * The two seven segment displays show the voltage difference on the AD11, AD10, AD2, AD3 pins in volts.
  * sw0 and sw1 select which channel to read from 

==== Features Used ====

|              ^ Not Used             ^ Used        ^
^ 16 user switches   |    |  X  |
^ 16 user LEDs |    |  X  |
^ Two tri-color LEDs  |  X  |    |
^ 5 User Push Buttons    |  X  |    |
^ Two 4-digit 7-segment displays   |    |  X  |
^ 4 Pmod ports   |  X  |    |
^ Pmod for XADC signals   |    |  X  |
^ 12-bit VGA output   |  X  |    |
^ USB-UART Bridge   |  X  |    |
^ Serial Flash for Application Data   |  X  |    |
^ USB HID Host With Mouse   |  X  |    |
^ USB HID Host With Keyboard   |  X  |    |
^ Micro SD card connector   |  X  |    |
^ PWM audio output   |  X  |    |
^ PDM microphone   |  X  |    |
^ 3-axis accelerometer   |  X  |    |
^ Temperature sensor   |  X  |    |
^ 10/100 Ethernet PHY   |  X  |    |

=== Extra Notes ===

A version of the project has been ported to ISE 14.7. The project file can be found {{:nexys4-ddr:isenexys4xadc.zip|here}}

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===== Prerequisites =====

===Hardware===
  * **Nexys 4 DDR FPGA board**
  * **Micro-USB cable**
  * **Wires and a voltage to measure** 

===Software===
  * **Vivado Design Suite 2016.4** 
    * //Newer versions can be used, but the procedure may vary slightly//
  * **Nexys 4 DDR Support Files** 
    * These files will describe GPIO interfaces on your board and make it easier to select your FPGA board and add GPIO IP blocks. 
    * Follow the Wiki guide: [[vivado:boardfiles|Vivado Board Files for Digilent 7-Series FPGA Boards]] on how to install Board Support Files for

-----

===== Downloads =====
Nexys 4 DDR Support Repository -- [[https://github.com/Digilent/Nexys-4-DDR-XADC/releases/download/v2016.4-1/Nexys-4-DDR-XADC-2016.4-1.zip|ZIP Archive]] [[https://github.com/Digilent/Nexys-4-DDR-XADC|GIT Repo]]

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===== Download and Launch the Nexys 4 DDR XADC Demo =====

>Follow the [[:learn:programmable-logic:tutorials:github-demos:start|Using Digilent Github Demo Projects]] Tutorial. This is an HDL design project, and as such does not support Vivado SDK, select the tutorial options appropriate for a Vivado-only design. As you will not need to set up your circuit to be measured until after the board is programmed, you do not need to return to this guide when prompted to check for extra hardware requirements and setup.

===== Using the Nexys 4 DDR XADC Demo =====

==== 1. Applying a Voltage to the XADC Port ====

>For this demo, the AD11P and AD11N pins are used on the JXADC header. We hooked up a signal generator to our pins. All of the other pins were grounded to avoid coupling.
>
>{{:nexys:nexys4:xadc11.jpg?300|}}  {{:nexys:nexys4:xadc10.jpg?300|}}


==== 2. 7-Segment Display and LEDs ====
>
>The 7-Segment display shows the current voltage across the selected xadc pins. The LEDs turn on from right to left as the input voltage increases.
>
>{{:nexys:nexys4:xadc4.jpg?300|}} {{:nexys:nexys4:xadc6.jpg?300|}}

==== 3. Selecting a Channel ====

>To view the level of a different XADC channel on the display and LEDs, change sw0 and sw1 to the desired channel number.

{{tag>learn programmable-logic project nexys-4-ddr}}