====== Arty Microblaze Base System Design ======

{{:arty:arty-obl-1000.png?600|}}

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===== Overview =====
==== Features Used ====

|                                  ^ Not Used  ^ Used  ^
^ 4 user switches                  |           |   X   |
^ 4 user LEDs                      |           |   X   |
^ 4 user RGB LEDs                  |           |   X   |
^ USB-UART Bridge                  |           |   X   |
^ 4 user push buttons              |           |   X   |
^ 10/100 Ethernet PHY              |           |   X   |
^ 256MB 800Mt/s DDR3 Memory        |           |   X   |
^ Serial Flash                     |           |   X   |
^ Four Pmod ports                  |     X     |       |
^ Shield Connector                 |           |   X   |


==== Description ====

This Vivado IP Integrator project implements a Microblaze system with cores that communicate with all of the peripherals on the Arty. This design can be used as a catch all hardware design for most Microblaze applications using ARTY. 

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===== Prerequisites =====

===Hardware===
  * **Arty FPGA board**
  * **Micro-USB cable**

===Software===
  * **Vivado Design Suite 2016.4** 
    * //Newer versions can be used, but the procedure may vary slightly//
    * Xilinx SDK 2016.4 must be included in the installation
  * **Digilent Board Support Files for Vivado** 
    * Follow the [[vivado:boardfiles|Vivado Board Files for Digilent 7-Series FPGA Boards]] guide on how to install Board Support Files for Vivado.

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===== Downloads =====

Arty Support Repository -- [[https://github.com/Digilent/Arty-BSD/archive/master.zip|ZIP]] [[https://github.com/Digilent/Arty-BSD|GIT Repo]]

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===== How to... =====



==== 1. Download the Project ====

>1.1) Download the project repo zip file which can be downloaded {{https://github.com/Digilent/Arty/archive/master.zip|here}}. Once you have downloaded the project, unzip it in the location of your choosing.

>1.2) If you want to generate the project in Vivado, continue to step 2. If you want to move straight to Xilinx SDK, skip to step 5.

==== 2. Generate the Project ====
>2.1) If not already installed, install the Vivado Board Files for the Arty by following this guide: [[vivado:boardfiles2015| Installing Vivado Board Files for Digilent Boards]].

>2.2) Generate the **bsd** project in the Projects folder by following this guide before continuing: [[vivado:github|How to Generate a Project from Digilent's Github]].

==== 3. Build the Project ====

>3.1) Click **Generate Bitstream** on the left hand menu towards the bottom. Vivado will run through both Run Synthesis and Run Implementation before it generates the bitstream automatically. 
>
>Note: If you want, you can click each step by itself in the order of **Run Synthesis**, **Run Implementation** and then **Generate Bitstream**.
>
>{{:basys3:buildflow.png?600|}}


==== 4. Export to SDK ====

>4.1) Export the microblaze project by going to **File>Export>Export Hardware**. Click the check box to Include the bitstream, and export it local to project. This will create a .sdk folder in your project directory. Afterwards, click **File>Launch SDK**. Both the exported location and workspace should be left as <Local to Project>. Click "OK" to launch Xilinx SDK.
>
>4.2) Skip to step 6.

==== 5. Open Xilinx SDK and create a workspace ====

>5.1) Open up Xilinx SDK and create a workspace where your project will be saved.
>
>{{:genesys2:1.jpg?500|}}

==== 6. Import the SDK files ====

>6.1) In your project Explorer window on the left side, click **File>Import**, then under the general folder, select Existing projects. (Or just click **Import Project** on the main screen).
>
>{{:genesys2:2.jpg?500|}}

>6.2) Navigate to where you saved the downloaded project, select the **sdk** folder, and click OK. In the //Import// window, click Finish to import the system hardware wrapper.
>
>{{:genesys2:3.jpg?300|}}

>6.3) Import the projects by clicking //Finish//. You can ignore the warnings that may pop up.
>
>{{:genesys2:4.jpg?500|}}

==== 7. Program the FPGA ====

>7.1) Click **Xilinx Tools>Program FPGA** and click **Program**. Xilinx SDK will then program the FPGA with a microblaze bit file.
>
>{{:genesys2:5.jpg?500|}}

==== 8. Program the Microblaze processor ====

>8.1) Right click on the **demo** folder and click  **Run as>Launch on Hardware(GDB)**. The microblaze program will be programmed onto your Nexys Video.
>
>{{:genesys2:6.jpg?500|}}

==== 9. Run the Project ====

This portion will help you run the demo and observe all its features. 

>9.1) Observe LED Blink
>
>The demo is running a simple blink on LED5. This behaves much like the arduino sketch blink.

/*{{tag>learn programmable-logic tutorial example arty}}*/