{"id":7388,"date":"2015-06-01T20:00:15","date_gmt":"2015-06-02T03:00:15","guid":{"rendered":"https:\/\/blog.digilentinc.com\/?p=7388"},"modified":"2025-01-30T15:19:39","modified_gmt":"2025-01-30T23:19:39","slug":"coding-logic-gates","status":"publish","type":"post","link":"https:\/\/digilent.com\/blog\/coding-logic-gates\/","title":{"rendered":"Coding Logic Gates"},"content":{"rendered":"<p>Earlier today, Josh\u00a0(a\u00a0fellow intern and blog contributor) wrote a <a href=\"https:\/\/digilent.com\/blog\/index.php\/logic-gates\/\">blog post about logic gates<\/a>. After reading through Josh&#8217;s post and gaining an understanding of the concepts and basic functions of those gates, I figured now would be the perfect time to learn some code. I am going to go over each logic gate and it&#8217;s code in <span style=\"color: #008000;\">Verilog<\/span> (a hardware language), <span style=\"color: #ff0000;\">VHDL<\/span> (another hardware language) and <span style=\"color: #800080;\">C<\/span> (software language). If you need a refresher on what a hardware language is, you can read about <a href=\"https:\/\/digilent.com\/blog\/verilog-vs-vhdl\/\" target=\"_blank\" rel=\"noopener\">Verilog vs. VHDL<\/a>. Each gate is shown below with the code for each language in their respective colors.<\/p>\n<p>&nbsp;<\/p>\n<p style=\"text-align: center;\"><strong>NOT:<\/strong><\/p>\n<figure id=\"attachment_7396\" aria-describedby=\"caption-attachment-7396\" style=\"width: 348px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2015\/06\/notdiff.png\"><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-7396\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2015\/06\/notdiff.png\" alt=\"The not gate.\" width=\"348\" height=\"115\" srcset=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2015\/06\/notdiff.png 348w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2015\/06\/notdiff-225x74.png 225w\" sizes=\"auto, (max-width: 348px) 100vw, 348px\" \/><\/a><figcaption id=\"caption-attachment-7396\" class=\"wp-caption-text\">The NOT\u00a0gate.<\/figcaption><\/figure>\n<p style=\"text-align: center;\"><span style=\"color: #008000;\">\u00a0 \u00a0 \u00a0assign Y = ~A;<\/span><\/p>\n<p style=\"text-align: center;\"><span style=\"color: #ff0000;\">\u00a0 \u00a0 \u00a0Y &lt;= NOT A;<\/span><\/p>\n<p style=\"text-align: center;\"><span style=\"color: #800080;\">\u00a0 \u00a0 \u00a0Y = !A;<\/span><\/p>\n<p style=\"text-align: center;\"><strong>AND:<\/strong><\/p>\n<figure id=\"attachment_7171\" aria-describedby=\"caption-attachment-7171\" style=\"width: 406px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2015\/05\/and2.png\"><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-7171\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2015\/05\/and2.png\" alt=\"The and gate.\" width=\"406\" height=\"103\" srcset=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2015\/05\/and2.png 406w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2015\/05\/and2-225x57.png 225w\" sizes=\"auto, (max-width: 406px) 100vw, 406px\" \/><\/a><figcaption id=\"caption-attachment-7171\" class=\"wp-caption-text\">The AND\u00a0gate.<\/figcaption><\/figure>\n<p style=\"text-align: center;\"><span style=\"color: #ff99cc;\"><span style=\"color: #008000;\">\u00a0 \u00a0 assign Y = A &amp; B<\/span>;<\/span><\/p>\n<p style=\"text-align: center;\"><span style=\"color: #ff0000;\">\u00a0 \u00a0 Y &lt;= A\u00a0AND\u00a0B;<\/span><\/p>\n<p style=\"text-align: center;\"><span style=\"color: #800080;\">\u00a0 \u00a0 Y\u00a0= A &amp;&amp; B;<\/span><\/p>\n<p style=\"text-align: center;\"><strong>NAND<\/strong>:<\/p>\n<figure id=\"attachment_7391\" aria-describedby=\"caption-attachment-7391\" style=\"width: 406px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2015\/06\/nandfix.png\"><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-7391\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2015\/06\/nandfix.png\" alt=\"The nand gate.\" width=\"406\" height=\"107\" srcset=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2015\/06\/nandfix.png 406w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2015\/06\/nandfix-225x59.png 225w\" sizes=\"auto, (max-width: 406px) 100vw, 406px\" \/><\/a><figcaption id=\"caption-attachment-7391\" class=\"wp-caption-text\">The NAND\u00a0gate.<\/figcaption><\/figure>\n<p style=\"text-align: center;\"><span style=\"color: #008000;\">\u00a0 \u00a0assign Y = ~(A &amp; B);<\/span><\/p>\n<p style=\"text-align: center;\"><span style=\"color: #ff0000;\">\u00a0 \u00a0Y &lt;= A NAND\u00a0B;<\/span><\/p>\n<p style=\"text-align: center;\"><span style=\"color: #800080;\">\u00a0 \u00a0Y = !(A &amp;&amp; B);<\/span><\/p>\n<p style=\"text-align: center;\"><strong>OR:<\/strong><\/p>\n<figure id=\"attachment_7197\" aria-describedby=\"caption-attachment-7197\" style=\"width: 406px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2015\/05\/or.png\"><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-7197\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2015\/05\/or.png\" alt=\"The or gate.\" width=\"406\" height=\"110\" srcset=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2015\/05\/or.png 406w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2015\/05\/or-225x61.png 225w\" sizes=\"auto, (max-width: 406px) 100vw, 406px\" \/><\/a><figcaption id=\"caption-attachment-7197\" class=\"wp-caption-text\">The OR\u00a0gate.<\/figcaption><\/figure>\n<p style=\"text-align: center;\"><span style=\"color: #008000;\">\u00a0 \u00a0assign Y = A|B;<\/span><\/p>\n<p style=\"text-align: center;\"><span style=\"color: #ff0000;\">\u00a0 \u00a0Y &lt;= A OR\u00a0B;<\/span><\/p>\n<p style=\"text-align: center;\"><span style=\"color: #800080;\">\u00a0 \u00a0Y = A || B;<\/span><\/p>\n<p style=\"text-align: center;\"><strong>NOR:<\/strong><\/p>\n<figure id=\"attachment_7392\" aria-describedby=\"caption-attachment-7392\" style=\"width: 406px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2015\/06\/norfix.png\"><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-7392\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2015\/06\/norfix.png\" alt=\"The nor gate.\" width=\"406\" height=\"115\" srcset=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2015\/06\/norfix.png 406w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2015\/06\/norfix-225x64.png 225w\" sizes=\"auto, (max-width: 406px) 100vw, 406px\" \/><\/a><figcaption id=\"caption-attachment-7392\" class=\"wp-caption-text\">The NOR\u00a0gate.<\/figcaption><\/figure>\n<p style=\"text-align: center;\"><span style=\"color: #008000;\">\u00a0 \u00a0 assign Y = ~(A|B);<\/span><\/p>\n<p style=\"text-align: center;\"><span style=\"color: #ff0000;\">\u00a0 \u00a0 Y &lt;= A NOR\u00a0B;<\/span><\/p>\n<p style=\"text-align: center;\"><span style=\"color: #800080;\">\u00a0 \u00a0 Y = ! (A || B);<\/span><\/p>\n<p style=\"text-align: center;\"><strong>XOR:<\/strong><\/p>\n<figure id=\"attachment_7201\" aria-describedby=\"caption-attachment-7201\" style=\"width: 406px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2015\/05\/xor.png\"><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-7201\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2015\/05\/xor.png\" alt=\"The xor gate.\" width=\"406\" height=\"115\" srcset=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2015\/05\/xor.png 406w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2015\/05\/xor-225x64.png 225w\" sizes=\"auto, (max-width: 406px) 100vw, 406px\" \/><\/a><figcaption id=\"caption-attachment-7201\" class=\"wp-caption-text\">The XOR\u00a0gate.<\/figcaption><\/figure>\n<p style=\"text-align: center;\"><span style=\"color: #008000;\">\u00a0 \u00a0assign Y = A^B;<\/span><\/p>\n<p style=\"text-align: center;\"><span style=\"color: #ff0000;\">\u00a0 \u00a0Y &lt;= A\u00a0XOR\u00a0B;<\/span><\/p>\n<p style=\"text-align: center;\"><span style=\"color: #800080;\">\u00a0 \u00a0Y = ((!A) &amp;&amp; B) || (A &amp;&amp; (!B));<\/span><\/p>\n<p style=\"text-align: center;\"><strong>XNOR:<\/strong><\/p>\n<figure id=\"attachment_7393\" aria-describedby=\"caption-attachment-7393\" style=\"width: 406px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2015\/06\/xnorfix.png\"><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-7393\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2015\/06\/xnorfix.png\" alt=\"The xnor gate.\" width=\"406\" height=\"115\" srcset=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2015\/06\/xnorfix.png 406w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2015\/06\/xnorfix-225x64.png 225w\" sizes=\"auto, (max-width: 406px) 100vw, 406px\" \/><\/a><figcaption id=\"caption-attachment-7393\" class=\"wp-caption-text\">The XNOR\u00a0gate.<\/figcaption><\/figure>\n<p style=\"text-align: center;\"><span style=\"color: #008000;\">\u00a0 \u00a0\u00a0assign Y = A^B;<\/span><\/p>\n<p style=\"text-align: center;\"><span style=\"color: #ff0000;\">\u00a0 \u00a0Y &lt;= A XNOR\u00a0B;<\/span><\/p>\n<p style=\"text-align: center;\"><span style=\"color: #800080;\">\u00a0 \u00a0Y = !((!A) &amp;&amp; B) || (A &amp;&amp; (!B));<\/span><\/p>\n<p style=\"text-align: left;\">As you can see from the examples of all of these gates, Verilog and VHDL aren&#8217;t all that different from C in terms of syntax. In fact, C has bitwise logic operators that are the same as those of the hardware languages. However, bitwise operations aren&#8217;t very common in C. Unfortunately, C doesn&#8217;t have a symbol for XOR and XNOR, so those had to be made out of AND, OR, and NOT\u00a0gates.<\/p>\n<p style=\"text-align: left;\">This content is relevant to the <a href=\"https:\/\/digilent.com\/shop\/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users\/\">Basys 3<\/a>, \u00a0<a href=\"https:\/\/digilent.com\/shop\/nexys-a7-fpga-trainer-board-recommended-for-ece-curriculum\/\">Nexys A7<\/a>, <a href=\"https:\/\/digilent.com\/shop\/cmod-a7-35t-breadboardable-artix-7-fpga-module\/\">Cmod A7<\/a>,\u00a0and <a href=\"https:\/\/digilent.com\/shop\/cmod-s7-breadboardable-spartan-7-fpga-module\/\">Cmod S7.<\/a> All can be found on our <a href=\"https:\/\/digilent.com\/shop\/about-system-boards-and-components\/#System\">FPGA product page<\/a>.<\/p>\n<div class='watch-action'><div class='watch-position align-left'><div class='action-like'><a class='lbg-style6 like-7388 jlk' data-task='like' data-post_id='7388' data-nonce='712f7a0d3d' rel='nofollow'><img src='https:\/\/digilent.com\/blog\/wp-content\/plugins\/wti-like-post-pro\/images\/pixel.gif' title='Like' \/><span class='lc-7388 lc'>+2<\/span><\/a><\/div><div class='action-unlike'><a class='unlbg-style6 unlike-7388 jlk' data-task='unlike' data-post_id='7388' data-nonce='712f7a0d3d' rel='nofollow'><img src='https:\/\/digilent.com\/blog\/wp-content\/plugins\/wti-like-post-pro\/images\/pixel.gif' title='Unlike' \/><span class='unlc-7388 unlc'>-2<\/span><\/a><\/div><\/div> <div class='status-7388 status align-left'><\/div><\/div><div class='wti-clear'><\/div>","protected":false},"excerpt":{"rendered":"<p>Earlier today, Josh (a fellow intern and blog contributor) wrote a blog post about logic gates. After reading through Josh&#8217;s post and gaining an understanding of the concepts and basic functions of those gates, I figured now would be the perfect time to learn some code. I am going to go over each logic gate and it&#8217;s code in Verilog (a hardware language), VHDL (another hardware language) and C (software language). <\/p>\n","protected":false},"author":18,"featured_media":7398,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_jetpack_newsletter_access":"","_jetpack_dont_email_post_to_subs":false,"_jetpack_newsletter_tier_id":0,"_jetpack_memberships_contains_paywalled_content":false,"_jetpack_feature_clip_id":0,"_jetpack_memberships_contains_paid_content":false,"footnotes":"","jetpack_post_was_ever_published":false,"_ppma_block_editor_authors":""},"categories":[4323,1563],"tags":[],"ppma_author":[4466],"class_list":["post-7388","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-software","category-guide"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v28.7 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Coding Logic Gates - Digilent Blog<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/digilent.com\/blog\/coding-logic-gates\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Coding Logic Gates - Digilent Blog\" \/>\n<meta property=\"og:description\" content=\"Earlier today, Josh (a fellow intern and blog contributor) wrote a blog post about logic gates. After reading through Josh&#039;s post and gaining an understanding of the concepts and basic functions of those gates, I figured now would be the perfect time to learn some code. I am going to go over each logic gate and it&#039;s code in Verilog (a hardware language), VHDL (another hardware language) and C (software language).\" \/>\n<meta property=\"og:url\" content=\"https:\/\/digilent.com\/blog\/coding-logic-gates\/\" \/>\n<meta property=\"og:site_name\" content=\"Digilent Blog\" \/>\n<meta property=\"article:published_time\" content=\"2015-06-02T03:00:15+00:00\" \/>\n<meta property=\"article:modified_time\" content=\"2025-01-30T23:19:39+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2015\/06\/feature.png\" \/>\n\t<meta property=\"og:image:width\" content=\"461\" \/>\n\t<meta property=\"og:image:height\" content=\"346\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/png\" \/>\n<meta name=\"author\" content=\"Kaitlyn Franz\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data1\" content=\"Kaitlyn Franz\" \/>\n\t<meta name=\"twitter:label2\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data2\" content=\"2 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\\\/\\\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\\\/\\\/digilent.com\\\/blog\\\/coding-logic-gates\\\/#article\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/digilent.com\\\/blog\\\/coding-logic-gates\\\/\"},\"author\":{\"name\":\"Kaitlyn Franz\",\"@id\":\"https:\\\/\\\/digilent.com\\\/blog\\\/#\\\/schema\\\/person\\\/7c1c4144d4cc194b2fef7858a83119b9\"},\"headline\":\"Coding Logic Gates\",\"datePublished\":\"2015-06-02T03:00:15+00:00\",\"dateModified\":\"2025-01-30T23:19:39+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\\\/\\\/digilent.com\\\/blog\\\/coding-logic-gates\\\/\"},\"wordCount\":385,\"commentCount\":2,\"image\":{\"@id\":\"https:\\\/\\\/digilent.com\\\/blog\\\/coding-logic-gates\\\/#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/digilent.com\\\/blog\\\/wp-content\\\/uploads\\\/2015\\\/06\\\/feature.png\",\"articleSection\":[\"Digilent Software Solutions: What They Are &amp; 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After reading through Josh's post and gaining an understanding of the concepts and basic functions of those gates, I figured now would be the perfect time to learn some code. I am going to go over each logic gate and it's code in Verilog (a hardware language), VHDL (another hardware language) and C (software language).","og_url":"https:\/\/digilent.com\/blog\/coding-logic-gates\/","og_site_name":"Digilent Blog","article_published_time":"2015-06-02T03:00:15+00:00","article_modified_time":"2025-01-30T23:19:39+00:00","og_image":[{"width":461,"height":346,"url":"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2015\/06\/feature.png","type":"image\/png"}],"author":"Kaitlyn Franz","twitter_card":"summary_large_image","twitter_misc":{"Written by":"Kaitlyn Franz","Est. reading time":"2 minutes"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"Article","@id":"https:\/\/digilent.com\/blog\/coding-logic-gates\/#article","isPartOf":{"@id":"https:\/\/digilent.com\/blog\/coding-logic-gates\/"},"author":{"name":"Kaitlyn Franz","@id":"https:\/\/digilent.com\/blog\/#\/schema\/person\/7c1c4144d4cc194b2fef7858a83119b9"},"headline":"Coding Logic Gates","datePublished":"2015-06-02T03:00:15+00:00","dateModified":"2025-01-30T23:19:39+00:00","mainEntityOfPage":{"@id":"https:\/\/digilent.com\/blog\/coding-logic-gates\/"},"wordCount":385,"commentCount":2,"image":{"@id":"https:\/\/digilent.com\/blog\/coding-logic-gates\/#primaryimage"},"thumbnailUrl":"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2015\/06\/feature.png","articleSection":["Digilent Software Solutions: What They Are &amp; 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