{"id":3481,"date":"2015-02-12T16:30:19","date_gmt":"2015-02-13T00:30:19","guid":{"rendered":"https:\/\/blog.digilentinc.com\/?p=3481"},"modified":"2025-01-03T00:39:30","modified_gmt":"2025-01-03T08:39:30","slug":"verilog-vs-vhdl","status":"publish","type":"post","link":"https:\/\/digilent.com\/blog\/verilog-vs-vhdl\/","title":{"rendered":"Verilog vs. VHDL"},"content":{"rendered":"

At this point in reading the blog and going through the Learn<\/a> material, you might realize that there is a lot of FPGA code. It doesn’t look like C, it doesn’t look like Java…what is it?<\/p>\n

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When learning FPGA design, there are two languages to choose\u00a0from, Verilog or\u00a0VHDL. They are called HDLs, or hardware design languages. Unlike a language like C, where they define what you want the circuit to do, HDLs define how the hardware needs to be configured. \u00a0Now, it’s not exactly as clear as that, as you can code behaviorally or structurally in HDL, but that’s the main idea.<\/p>\n

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So if you want to program FPGAs, which do you use?<\/p>\n

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I use Verilog, but that’s only because that’s what I was taught. The languages are very close, so once you learn one it’s not to hard to learn the other. Thus,\u00a0picking one to learn first is not that big of a decision. But if you are concerned about it, the\u00a0general consensus is that it is much easier to learn VHDL and then learn Verilog<\/a>, because VHDL is the harder language to learn. However if you’ve already learned Verilog, I wouldn’t be too discouraged.<\/p>\n

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They also say that is easier to Learn C, then C++, then Java, but I did it in the reverse\u00a0order and it wasn’t too bad. Another consideration is that in most industries other than defense, it is more common to use Verilog, so if you know what industry you want to work in,\u00a0you could learn the one that they use.<\/p>\n

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The differences in usage and the differences in the languages stem from the history of their creation. VHDL was written as a description language, whereas Verilog was written as a hardware modeling language. As a result, VHDL is a strongly typed, verbose, deterministic language. Verilog, being the opposite in terms of its features,\u00a0looks similar to C code, which is why it is often easier to learn.<\/p>\n

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Here is an example of both languages.<\/p>\n

\"Verilog<\/a>
Verilog and VHDL code to implement a mux.<\/figcaption><\/figure>\n