{"id":32193,"date":"2026-04-15T09:55:21","date_gmt":"2026-04-15T16:55:21","guid":{"rendered":"https:\/\/digilent.com\/blog\/?p=32193"},"modified":"2026-04-15T09:55:21","modified_gmt":"2026-04-15T16:55:21","slug":"using-a-cpu-clock-for-clean-bus-captures-with-digital-discovery-from-the-forum","status":"publish","type":"post","link":"https:\/\/digilent.com\/blog\/using-a-cpu-clock-for-clean-bus-captures-with-digital-discovery-from-the-forum\/","title":{"rendered":"Using a CPU Clock for Clean Bus Captures with Digital Discovery: From the Forum"},"content":{"rendered":"<h4><strong>The Question<\/strong><\/h4>\n<div>\n<p>A Digilent forum user working on a vintage computing project needed to troubleshoot hardware built around a <strong>6502 CPU<\/strong>. Their goal was to extract the CPU\u2019s <strong>address and data bus activity<\/strong> using a <strong>Digital Discovery<\/strong> logic analyzer and export that activity as easy\u2011to\u2011read hexadecimal values.<\/p>\n<p>While the signals displayed correctly in WaveForms, capturing data at a high internal sample rate quickly became unmanageable. Large acquisitions caused WaveForms to slow down or freeze &#8211; particularly in the <strong>Events<\/strong> tab &#8211; and the resulting data sets were far too large to meaningfully analyze or export.<\/p>\n<p>What the user really wanted was simpler: <strong>capture one meaningful snapshot per CPU clock cycle.<\/strong><\/p>\n<hr \/>\n<h2>The Challenge<\/h2>\n<p>Sampling the bus using the Digital Discovery\u2019s internal clock resulted in:<\/p>\n<ul>\n<li>An extremely large number of samples captured at a high rate<\/li>\n<li>Increased memory usage inside WaveForms<\/li>\n<li>Long, repetitive logs where bus values were repeated for hundreds of samples<\/li>\n<\/ul>\n<p>This made it difficult (or impossible) to identify individual bus transactions or export clean, human\u2011readable data.<\/p>\n<hr \/>\n<h4>The Answer: Use the CPU Clock as the Sample Clock<\/h4>\n<p>Instead of sampling continuously at a high internal rate, the Logic Analyzer can be configured to sample synchronously using an external signal, in this case, the CPU\u2019s own clock.<\/p>\n<p>By telling the Digital Discovery to sample only on each rising or falling edge of the CPU clock, the capture is reduced to exactly one sample per clock cycle.<\/p>\n<p>This approach:<\/p>\n<ul>\n<li>Dramatically reduces the total number of samples<\/li>\n<li>Minimizes memory usage in WaveForms<\/li>\n<li>Produces bus captures that align cleanly with CPU operation<\/li>\n<\/ul>\n<p>Rather than recording a dense stream of redundant data, the logic analyzer now records only when the CPU updates its address and data buses.<\/p>\n<hr \/>\n<h4>How to Set It Up in WaveForms<\/h4>\n<ol>\n<li>\n<h6><strong>Connect Your Signals<\/strong><\/h6>\n<ul>\n<li>Connect the address bus, data bus, and control signals (RW, RESET, etc.) to the Digital Discovery\u2019s logic inputs<\/li>\n<li>Connect the CPU clock to its own dedicated logic input pin<\/li>\n<\/ul>\n<\/li>\n<li>\n<h6><strong>Configure the Logic Analyzer<\/strong><\/h6>\n<ul>\n<li>Open the <strong>Logic Analyzer<\/strong> instrument<\/li>\n<li>Click the <strong>gear icon<\/strong> on the right side of the control panel<\/li>\n<li>Under <strong>Sampling<\/strong>, change the source from <em>Internal<\/em> to the pin connected to the CPU clock (for example, DIN0)<\/li>\n<li>Select the appropriate <strong>edge<\/strong> (rising or falling), based on when your CPU\u2019s bus data is valid<\/li>\n<li>Set the <strong>Rate<\/strong> to at least <strong>2\u00d7 the CPU clock frequency<\/strong> so the Digital Discovery can reliably detect each edge<\/li>\n<\/ul>\n<\/li>\n<li>\n<h6><strong>Reduce the Sample Count<\/strong><\/h6>\n<ul>\n<li>Since you\u2019re now sampling only on clock edges, you can significantly lower the total sample count while still capturing meaningful activity<\/li>\n<\/ul>\n<\/li>\n<\/ol>\n<hr \/>\n<h4>Cleaning Up the View<\/h4>\n<p>To make the captured data easier to read in WaveForms:<\/p>\n<ul>\n<li>Open the <strong>plot gear icon<\/strong> at the top of the Logic Analyzer<\/li>\n<li>Under <strong>Global Options<\/strong>, change <strong>Vertical<\/strong> from the default triangular display to <strong>Logic Edges<\/strong><\/li>\n<\/ul>\n<p>This presents clean, vertical transitions and makes address and data changes much easier to follow.<\/p>\n<hr \/>\n<h4>Exporting the Data<\/h4>\n<p>Once captured, exporting the data is straightforward:<\/p>\n<ul>\n<li>Go to <strong>File \u2192 Export \u2192 Logic Analyzer Data<\/strong><\/li>\n<li>Select only the signals you want to include<\/li>\n<li>Choose a hexadecimal format for address and data lines<\/li>\n<li>Export to CSV<\/li>\n<\/ul>\n<p>The result is a compact, readable log of CPU activity, exactly what\u2019s needed for tracing bus behavior during debugging.<\/p>\n<hr \/>\n<h4>Takeaway<\/h4>\n<p>Using an external clock for synchronous sampling turns the Digital Discovery into a powerful tool for CPU and bus analysis. By sampling only on meaningful clock edges, you avoid excessive data, reduce memory usage, and gain clear insight into system behavior, one clock cycle at a time.<\/p>\n<p>This same technique can be applied to microcontrollers, FPGAs, and other clocked digital systems where clarity matters more than raw sample rate.<\/p>\n<p>View the full forum thread <a href=\"https:\/\/forum.digilent.com\/topic\/33293-waveforms-functionalities-without-an-external-cpu\/\">HERE<\/a>.<\/p>\n<\/div>\n<div class='watch-action'><div class='watch-position align-left'><div class='action-like'><a class='lbg-style6 like-32193 jlk' data-task='like' data-post_id='32193' data-nonce='4d1b41d1d7' rel='nofollow'><img src='https:\/\/digilent.com\/blog\/wp-content\/plugins\/wti-like-post-pro\/images\/pixel.gif' title='Like' \/><span class='lc-32193 lc'>0<\/span><\/a><\/div><div class='action-unlike'><a class='unlbg-style6 unlike-32193 jlk' data-task='unlike' data-post_id='32193' data-nonce='4d1b41d1d7' rel='nofollow'><img src='https:\/\/digilent.com\/blog\/wp-content\/plugins\/wti-like-post-pro\/images\/pixel.gif' title='Unlike' \/><span class='unlc-32193 unlc'>0<\/span><\/a><\/div><\/div> <div class='status-32193 status align-left'>Be the 1st to vote.<\/div><\/div><div class='wti-clear'><\/div>","protected":false},"excerpt":{"rendered":"<p>The Question A Digilent forum user working on a vintage computing project needed to troubleshoot hardware built around a 6502 CPU. Their goal was to extract the CPU\u2019s address and &hellip; <\/p>\n","protected":false},"author":47,"featured_media":32311,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0,"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[20,1563,1561],"tags":[5284,5283,5279,5280,5282,5093,4562,5281,4380,5137,452],"ppma_author":[4587],"class_list":["post-32193","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-products","category-guide","category-applications","tag-bus-captures","tag-clean-bus","tag-cpu","tag-cpu-clock","tag-digital-discovery","tag-forum","tag-logic-analyzer","tag-sample","tag-sampling","tag-user-question","tag-waveforms"],"jetpack_featured_media_url":"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2026\/01\/FTF-CPU_Clock-735x400-1.png","jetpack_sharing_enabled":true,"authors":[{"term_id":4587,"user_id":0,"is_guest":1,"slug":"digilent","display_name":"Digilent","avatar_url":"https:\/\/secure.gravatar.com\/avatar\/?s=96&d=mm&r=g","1":"","2":"","3":"","4":"","5":"","6":"","7":"","8":"","9":"","10":""}],"post_mailing_queue_ids":[],"_links":{"self":[{"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/posts\/32193","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/users\/47"}],"replies":[{"embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/comments?post=32193"}],"version-history":[{"count":2,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/posts\/32193\/revisions"}],"predecessor-version":[{"id":32333,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/posts\/32193\/revisions\/32333"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/media\/32311"}],"wp:attachment":[{"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/media?parent=32193"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/categories?post=32193"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/tags?post=32193"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/ppma_author?post=32193"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}