{"id":30845,"date":"2024-07-16T18:51:42","date_gmt":"2024-07-17T01:51:42","guid":{"rendered":"https:\/\/digilent.com\/blog\/?p=30845"},"modified":"2025-01-14T16:06:51","modified_gmt":"2025-01-15T00:06:51","slug":"vcos-mmcms-plls-and-cmts-clocking-resources-on-fpga-boards","status":"publish","type":"post","link":"https:\/\/digilent.com\/blog\/vcos-mmcms-plls-and-cmts-clocking-resources-on-fpga-boards\/","title":{"rendered":"VCOs, MMCMs, PLLs, and CMTs \u2013 Clocking Resources on FPGA Boards"},"content":{"rendered":"<p><span data-contrast=\"auto\">Let\u2019s talk about clocking. It\u2019s crucial to the functionality of FPGA boards and digital design in general, as all synchronous logic depends on clocks. In this article, we\u2019ll define some terms, briefly discuss the architecture of a 7-series CMT, and then preview a practical example of how we can mess around with an output clock, changing the frequency during runtime.<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:278}\">\u00a0<\/span><\/p>\n<ul>\n<li data-leveltext=\"\uf0b7\" data-font=\"Symbol\" data-listid=\"1\" data-list-defn-props=\"{&quot;335551671&quot;:0,&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;\uf0b7&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}\" aria-setsize=\"-1\" data-aria-posinset=\"0\" data-aria-level=\"1\"><i><span data-contrast=\"auto\">Clock Dividers<\/span><\/i><span data-contrast=\"auto\"> are a fundamental concept \u2013 a simple counter can be used to cleanly divide a clock. For example, counting from 0 \u2013 4 and toggling divides a clock by 10 (as below). For routing reasons, it\u2019s best to avoid implementing a true clock divider in an FPGA, but FPGAs still make use of built-in clock dividers.<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:278}\">\u00a0<\/span><\/li>\n<\/ul>\n<p><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335551550&quot;:2,&quot;335551620&quot;:2,&quot;335559739&quot;:160,&quot;335559740&quot;:278}\"><a href=\"https:\/\/digilent.com\/blog\/vcos-mmcms-plls-and-cmts-clocking-resources-on-fpga-boards\/wavedrom\/\" rel=\"attachment wp-att-30847\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2024\/07\/wavedrom.png\" alt=\"\" width=\"560\" height=\"90\" class=\"alignnone size-full wp-image-30847\" \/><\/a>\u00a0<\/span><\/p>\n<p>&nbsp;<\/p>\n<ul>\n<li data-leveltext=\"\uf0b7\" data-font=\"Symbol\" data-listid=\"1\" data-list-defn-props=\"{&quot;335551671&quot;:0,&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;\uf0b7&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}\" aria-setsize=\"-1\" data-aria-posinset=\"1\" data-aria-level=\"1\"><i><span data-contrast=\"auto\">Voltage Controlled Oscillators<\/span><\/i><span data-contrast=\"auto\"> (VCOs) are a programmable type of clock source \u2013 put simply, a specific voltage level applied to the input of a VCO produces a corresponding frequency. Changing that voltage level based on certain conditions thus changes the clock.<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:278}\">\u00a0<\/span><\/li>\n<\/ul>\n<ul>\n<li data-leveltext=\"\uf0b7\" data-font=\"Symbol\" data-listid=\"1\" data-list-defn-props=\"{&quot;335551671&quot;:0,&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;\uf0b7&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}\" aria-setsize=\"-1\" data-aria-posinset=\"2\" data-aria-level=\"1\"><i><span data-contrast=\"auto\">Phase Frequency Detectors<\/span><\/i><span data-contrast=\"auto\"> (PFDs) are used in conjunction with other signal conditioning circuitry to generate a signal for a VCO, by adjusting the frequency and phase until a clock fed back from its VCO matches a reference clock.<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:278}\">\u00a0<\/span><\/li>\n<\/ul>\n<ul>\n<li data-leveltext=\"\uf0b7\" data-font=\"Symbol\" data-listid=\"1\" data-list-defn-props=\"{&quot;335551671&quot;:0,&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;\uf0b7&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}\" aria-setsize=\"-1\" data-aria-posinset=\"3\" data-aria-level=\"1\"><i><span data-contrast=\"auto\">Phase-Locked Loops<\/span><\/i><span data-contrast=\"auto\"> (PLLs) and <\/span><i><span data-contrast=\"auto\">Mixed-Mode Clock Manager<\/span><\/i><span data-contrast=\"auto\"> (MMCMs) are two similar architectures used in AMD FPGAs to take a reference clock and use it to consistently generate new clocks with various frequency and phase relationships to each other.<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:278}\">\u00a0<\/span><\/li>\n<\/ul>\n<ul>\n<li data-leveltext=\"\uf0b7\" data-font=\"Symbol\" data-listid=\"1\" data-list-defn-props=\"{&quot;335551671&quot;:0,&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;\uf0b7&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}\" aria-setsize=\"-1\" data-aria-posinset=\"4\" data-aria-level=\"1\"><i><span data-contrast=\"auto\">Clock Buffers<\/span><\/i><span data-contrast=\"auto\"> (BUFG, BUFR, etc) are a broad topic but generally are used to route clocks to and from different areas of an FPGA chip. As an aside, routing was mentioned earlier, and is a huge topic that this post won\u2019t get into. Perhaps another time.<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:278}\">\u00a0<\/span><\/li>\n<\/ul>\n<ul>\n<li data-leveltext=\"\uf0b7\" data-font=\"Symbol\" data-listid=\"1\" data-list-defn-props=\"{&quot;335551671&quot;:0,&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;\uf0b7&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}\" aria-setsize=\"-1\" data-aria-posinset=\"5\" data-aria-level=\"1\"><i><span data-contrast=\"auto\">Clock Management Tiles<\/span><\/i><span data-contrast=\"auto\"> (CMTs) are the name that AMD uses for hardware built into their FPGAs\u2019 that is dedicated to clocking. On 7-series parts, like those commonly used on our FPGA boards, these consist of an MMCM and a PLL.<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:278}\">\u00a0<\/span><\/li>\n<\/ul>\n<p><span data-contrast=\"auto\">It should be said, that while most of this is critical information for complex projects, AMD provides an IP called the <\/span><i><span data-contrast=\"auto\">Clocking Wizard<\/span><\/i><span data-contrast=\"auto\">, which automatically handles much of the configuration of CMTs in your projects \u2013 new users need not fear (at least keep the fear to a healthy level).<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:278}\">\u00a0<\/span><\/p>\n<p><span data-contrast=\"auto\">For extensive detail on clocking resources available in 7 series parts, check out UG472 \u2013\u00a0<\/span><span data-contrast=\"auto\"><a href=\"https:\/\/docs.amd.com\/v\/u\/en-US\/ug472_7Series_Clocking\">7 Series Clocking<\/a><\/span><\/p>\n<p><span data-contrast=\"auto\">To break down a 7-series MMCM, take a look at this diagram from UG472:<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:278}\">\u00a0<\/span><\/p>\n<p><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:278}\"> <a href=\"https:\/\/digilent.com\/blog\/vcos-mmcms-plls-and-cmts-clocking-resources-on-fpga-boards\/mmcm-architecture\/\" rel=\"attachment wp-att-30848\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2024\/07\/mmcm-architecture-600x409.png\" alt=\"\" width=\"600\" height=\"409\" class=\"alignnone size-medium wp-image-30848\" srcset=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2024\/07\/mmcm-architecture-600x409.png 600w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2024\/07\/mmcm-architecture-135x93.png 135w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2024\/07\/mmcm-architecture.png 975w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><\/a><\/span><\/p>\n<p><span data-contrast=\"auto\">A clock input is passed to an MMCM and can then be divided down (block \u201cD\u201d). Alongside a feedback clock, this clock is passed into a PFD. When combined with another clock divider between the VCO and feedback, this functionally lets us multiply the input clock by a programmable value. Additional fractional divide stages for each of the other clock outputs let us generate a wide variety of different frequencies with one CMT at the same time.<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:278}\">\u00a0<\/span><\/p>\n<p><span data-contrast=\"auto\">Functionally, the frequency of any particular output clock can be expressed as the frequency of the input clock, divided by a single programmable constant, multiplied by a fractional value, and then divided again by another fractional value:<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:278}\">\u00a0<\/span><\/p>\n<ul>\n<li data-leveltext=\"\uf0b7\" data-font=\"Symbol\" data-listid=\"3\" data-list-defn-props=\"{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;\uf0b7&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}\" aria-setsize=\"-1\" data-aria-posinset=\"1\" data-aria-level=\"1\"><span data-contrast=\"auto\">F<\/span><span data-contrast=\"auto\">VCO<\/span><span data-contrast=\"auto\"> = F<\/span><span data-contrast=\"auto\">CLKIN1<\/span><span data-contrast=\"auto\"> * CLKFBOUT_MULT \/ DIVCLK_DIVIDE<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:278}\">\u00a0<\/span><\/li>\n<\/ul>\n<ul>\n<li data-leveltext=\"\uf0b7\" data-font=\"Symbol\" data-listid=\"3\" data-list-defn-props=\"{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;\uf0b7&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}\" aria-setsize=\"-1\" data-aria-posinset=\"2\" data-aria-level=\"1\"><span data-contrast=\"auto\">F<\/span><span data-contrast=\"auto\">CLKOUT1<\/span><span data-contrast=\"auto\"> = F<\/span><span data-contrast=\"auto\">VCO<\/span><span data-contrast=\"auto\"> \/ CLKOUT#_DIVIDE<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:278}\">\u00a0<\/span><\/li>\n<\/ul>\n<p><span data-contrast=\"auto\">Where the following are values that can be set in programmable registers:<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:278}\">\u00a0<\/span><\/p>\n<ul>\n<li data-leveltext=\"\uf0b7\" data-font=\"Symbol\" data-listid=\"2\" data-list-defn-props=\"{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;\uf0b7&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}\" aria-setsize=\"-1\" data-aria-posinset=\"1\" data-aria-level=\"1\"><span data-contrast=\"auto\">CLKFBOUT_MULT \u2013 the feedback clock multiplier \u2013 is a fractional number with 8-bit integer component (0-255) and fractional component ranging from 0.000 to 0.999. Used in block \u201cM\u201d, above.<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:278}\">\u00a0<\/span><\/li>\n<\/ul>\n<ul>\n<li data-leveltext=\"\uf0b7\" data-font=\"Symbol\" data-listid=\"2\" data-list-defn-props=\"{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;\uf0b7&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}\" aria-setsize=\"-1\" data-aria-posinset=\"2\" data-aria-level=\"1\"><span data-contrast=\"auto\">DIVCLK_DIVIDE is an 8-bit integer in range 0-255, the value used in clock divider \u201cD\u201d, above.<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:278}\">\u00a0<\/span><\/li>\n<\/ul>\n<ul>\n<li data-leveltext=\"\uf0b7\" data-font=\"Symbol\" data-listid=\"2\" data-list-defn-props=\"{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;\uf0b7&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}\" aria-setsize=\"-1\" data-aria-posinset=\"3\" data-aria-level=\"1\"><span data-contrast=\"auto\">CLKOUT#_DIVIDE is a fractional number with 8-bit integer component (0-255) and fractional component ranging from 0.000 to 0.999. Each output clock\u2019s divider (blocks O0-O6) can be separately programmed.<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:278}\">\u00a0<\/span><\/li>\n<\/ul>\n<p><span data-contrast=\"auto\">Not all combinations of values that can be programmed into registers result in valid clocks that can actually run in an FPGA. AC\/DC switching characteristics documents for each AMD FPGA family, like <a href=\"https:\/\/docs.amd.com\/r\/en-US\/ds189-spartan-7-data-sheet\">DS189,<\/a><\/span><span data-contrast=\"auto\">\u00a0specify minimum and maximum frequencies for each device. For example, MMCM_F<\/span><span data-contrast=\"auto\">VCOMAX<\/span><span data-contrast=\"auto\">, the maximum VCO output frequency, for Spartan-7 speed grade -1 parts, like the one found on the Arty S7-50, is 1200 MHz.<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:278}\"> The settings that produce good clocks can be pretty narrow &#8211; for a full description of the process of picking values that will work, check out the &#8220;MMCM\/PLL Programming&#8221; section of <a href=\"https:\/\/docs.amd.com\/v\/u\/en-US\/ug472_7Series_Clocking\">UG472<\/a>.<\/span><\/p>\n<p><span data-contrast=\"auto\">We won\u2019t get into it here, but phases are similarly programmable. Note that the \u201cPhase Duty Cycle Config\u201d setting in the Clocking Wizard\u2019s Clocking Options tab needs to be checked to be able to reprogram clock phases and duty cycles.<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:278}\">\u00a0<\/span><\/p>\n<p><span data-contrast=\"auto\">In an upcoming blog post, we\u2019ll be putting some of these resources to the test. We created a testbed that allows for automatic control of a clock, by exposing the AXI4-Lite interface of a Clocking Wizard to a serial port. This allows us to read and write its registers from a host computer, remotely changing the frequencies and phases of the clocks that the CMT is outputting. These clocks are used to drive several registers, whose outputs are directed to Pmod ports so that they can be viewed on an oscilloscope. Sources for the testbed, built for our <a href=\"https:\/\/digilent.com\/shop\/arty-s7-spartan-7-fpga-development-board\/\">Arty S7-50 <\/a><\/span><span data-contrast=\"auto\">FPGA development board, are now available on our GitHub, described on this reference page: <a href=\"https:\/\/digilent.com\/reference\/programmable-logic\/arty-s7\/demos\/clocking\">Arty S7-50 Clocking Wizard Testbed<\/a><\/span><\/p>\n<p><span data-contrast=\"auto\">Its architecture is roughly as follows:<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:278}\">\u00a0<\/span><\/p>\n<p><span data-contrast=\"auto\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2024\/07\/uart_to_axi_bridge-1.png\" alt=\"\" width=\"1215\" height=\"313\" class=\"alignnone wp-image-30860\" srcset=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2024\/07\/uart_to_axi_bridge-1.png 1816w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2024\/07\/uart_to_axi_bridge-1-600x155.png 600w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2024\/07\/uart_to_axi_bridge-1-1024x264.png 1024w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2024\/07\/uart_to_axi_bridge-1-1536x396.png 1536w\" sizes=\"auto, (max-width: 1215px) 100vw, 1215px\" \/><\/span><\/p>\n<p><span data-contrast=\"auto\">Commands are received from a PC via UART, either from a Pmod pin or from USBUART. They consist of a single \u201cr\u201dead or \u201cw\u201drite byte, two address bytes, and four data bytes. Once a command has been collected, a custom controller translates these commands into AXI4-Lite transactions with the Clocking Wizard, potentially setting some register\u2019s value or returning some data back to the host. Some example commands are shown in a Python script, which can also be found through the reference page, used to control the USBUART serial port. More info on the Clocking Wizard\u2019s address space and register map can be found in AMD\u2019s product guide for the IP, [Clocking Wizard LogiCORE IP Product Guide<a href=\"https:\/\/docs.amd.com\/r\/en-US\/pg065-clk-wiz\"> PG065<\/a><\/span><span data-contrast=\"auto\">. <\/span><span data-contrast=\"auto\">It should be noted that since toggling registers are used at the outputs, frequencies of signals output by this testbed are divided down by a factor of two further than the MMCM outputs described above \u2013 expected phase differences between edges are also affected!<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:278}\">\u00a0<\/span><\/p>\n<p><span data-contrast=\"auto\">For a quick sample of what a clock output looks like, complete with frequency and phase offset measurements, this screenshot was captured using an Analog Discovery 3. Note the substantial overshoot in clock edges \u2013 this could be due to the use of flywires for analog input, and properly-compensated BNC scope probes could help.<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:278}\">\u00a0<\/span><\/p>\n<p><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:278}\"> <a href=\"https:\/\/digilent.com\/blog\/vcos-mmcms-plls-and-cmts-clocking-resources-on-fpga-boards\/waveforms-2\/\" rel=\"attachment wp-att-30850\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2024\/07\/waveforms-2-600x356.png\" alt=\"\" width=\"600\" height=\"356\" class=\"alignnone size-medium wp-image-30850\" srcset=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2024\/07\/waveforms-2-600x356.png 600w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2024\/07\/waveforms-2-1024x608.png 1024w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2024\/07\/waveforms-2.png 1102w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><\/a><\/span><\/p>\n<p>&nbsp;<\/p>\n<p><span data-contrast=\"auto\">Stay tuned for some captures of these clock signals with a higher-bandwidth scope<\/span><span data-contrast=\"auto\">!<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:278}\">\u00a0<\/span><\/p>\n<div class='watch-action'><div class='watch-position align-left'><div class='action-like'><a class='lbg-style6 like-30845 jlk' data-task='like' data-post_id='30845' data-nonce='e5335d04d0' rel='nofollow'><img src='https:\/\/digilent.com\/blog\/wp-content\/plugins\/wti-like-post-pro\/images\/pixel.gif' title='Like' \/><span class='lc-30845 lc'>+1<\/span><\/a><\/div><div class='action-unlike'><a class='unlbg-style6 unlike-30845 jlk' data-task='unlike' data-post_id='30845' data-nonce='e5335d04d0' rel='nofollow'><img src='https:\/\/digilent.com\/blog\/wp-content\/plugins\/wti-like-post-pro\/images\/pixel.gif' title='Unlike' \/><span class='unlc-30845 unlc'>0<\/span><\/a><\/div><\/div> <div class='status-30845 status align-left'><\/div><\/div><div class='wti-clear'><\/div>","protected":false},"excerpt":{"rendered":"<p>Let\u2019s talk about clocking. It\u2019s crucial to the functionality of FPGA boards and digital design in general, as all synchronous logic depends on clocks. In this article, we\u2019ll define some &hellip; <\/p>\n","protected":false},"author":52,"featured_media":30846,"comment_status":"open","ping_status":"open","sticky":true,"template":"","format":"standard","meta":{"footnotes":""},"categories":[35,1563,1561],"tags":[4911,4909,4433,4917,4923,4918,4908,4903,4914,4900,4910,4927,4901,1662,4913,4925,4606,4912,4907,4905,4921,4906,4919,4926,4920,4916,4902,4922,4563,4924,4915,4904],"ppma_author":[4462],"class_list":["post-30845","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-fpga","category-guide","category-applications","tag-7-series-cmt","tag-amd-fpgas","tag-analog-discovery-3","tag-arty-s7-50","tag-arty-s7-50-clocking-wizard-testbed","tag-axi4-lite-interface","tag-clock-buffers","tag-clock-dividers","tag-clock-frequency","tag-clocking","tag-clocking-wizard","tag-clocking-wizard-logicore-ip-product-guide","tag-digital-design","tag-fpga","tag-fractional-divide-stages","tag-frequency-control","tag-github","tag-mmcm-architecture","tag-mmcms","tag-pfds","tag-phase-duty-cycle","tag-plls","tag-pmod-ports","tag-python-script","tag-reference-clock","tag-spartan-7","tag-synchronous-logic","tag-testbed","tag-uart","tag-uart_to_axi_bridge","tag-ug472","tag-voltage-controlled-oscillators"],"jetpack_featured_media_url":"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2024\/07\/2024-July-Newsletter-ClockingResources-290x150-1.png","authors":[{"term_id":4462,"user_id":52,"is_guest":0,"slug":"abrown","display_name":"Arthur Brown","avatar_url":"https:\/\/secure.gravatar.com\/avatar\/0157dde33e86ff2f253098657a5a774e?s=96&d=mm&r=g","author_category":"","user_url":"","last_name":"Brown","last_name_2":"","first_name":"Arthur","first_name_2":"","job_title":"","description":""}],"post_mailing_queue_ids":[],"_links":{"self":[{"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/posts\/30845","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/users\/52"}],"replies":[{"embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/comments?post=30845"}],"version-history":[{"count":6,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/posts\/30845\/revisions"}],"predecessor-version":[{"id":30861,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/posts\/30845\/revisions\/30861"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/media\/30846"}],"wp:attachment":[{"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/media?parent=30845"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/categories?post=30845"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/tags?post=30845"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/ppma_author?post=30845"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}