{"id":28979,"date":"2022-03-28T09:40:26","date_gmt":"2022-03-28T16:40:26","guid":{"rendered":"https:\/\/digilent.com\/blog\/?p=28979"},"modified":"2023-02-07T17:25:01","modified_gmt":"2023-02-08T01:25:01","slug":"engineers-in-the-wild-preparing-a-vivado-project-for-i-o-characterization","status":"publish","type":"post","link":"https:\/\/digilent.com\/blog\/engineers-in-the-wild-preparing-a-vivado-project-for-i-o-characterization\/","title":{"rendered":"Engineers in the Wild: Preparing a Vivado Project for I\/O Characterization"},"content":{"rendered":"<p><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter size-full wp-image-28980\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/EngineersInTheWild-Post-7.png\" alt=\"\" width=\"580\" height=\"300\" data-wp-pid=\"28980\" \/><\/p>\n<p><em>Editor&#8217;s Note &#8211; In this series, we will take a behind the scenes look at how an engineer tackles a project from beginning to end. What challenges will come up? How can we face problems and come up with solutions? Aside from project completion, what are successes that we can celebrate along the way?<\/em><\/p>\n<ul>\n<li><em><a href=\"https:\/\/digilent.com\/blog\/engineers-in-the-wild-introducing-ryan-damato\/\">Post 1 &#8211; Introducing Ryan<\/a><\/em><\/li>\n<li><em><a href=\"https:\/\/digilent.com\/blog\/engineers-in-the-wild-wireless-radio-frequency-circuit-design-initial-considerations\/\">Post 2 &#8211; Initial Considerations<\/a><\/em><\/li>\n<li><em><a href=\"https:\/\/digilent.com\/blog\/engineers-in-the-wild-designing-a-zmod-peripheral\/\">Post 3 &#8211; Designing a Zmod Peripheral<\/a><\/em><\/li>\n<li><a href=\"https:\/\/digilent.com\/blog\/engineers-in-the-wild-setting-up-syzygy-dna-data\/\"><em>Post 4 &#8211; Setting Up SYZYGY DNA<\/em><\/a><\/li>\n<li><em><a href=\"https:\/\/digilent.com\/blog\/engineers-in-the-wild-writing-syzygy-dna-using-the-adp3450\/\">Post 5 &#8211; Writing SYZYGY DNA Using the ADP3450<\/a><\/em><\/li>\n<li><em><a href=\"https:\/\/digilent.com\/blog\/engineers-in-the-wild-packaging-an-ip-in-vivado\/\">Post 6 &#8211; Packing an IP in Vivado<\/a><\/em><\/li>\n<\/ul>\n<h2>Preparing a Vivado Project<\/h2>\n<p>In this entry of &#8220;Engineers in the Wild&#8221;, a project in Vivado will be created. The design will make use of the IP packaged in the previous entry in order to test the I\/Os on the designed Zmods. The below figures illustrate the create project wizard and the chosen setting in<a href=\"https:\/\/www.xilinx.com\/support\/download.html\"> Vivado 2021.1<\/a>.<\/p>\n<figure id=\"attachment_28981\" aria-describedby=\"caption-attachment-28981\" style=\"width: 600px\" class=\"wp-caption aligncenter\"><img loading=\"lazy\" decoding=\"async\" class=\"size-medium wp-image-28981\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-7-Figure-1-New-Project-Wizard-600x418.png\" alt=\"\" width=\"600\" height=\"418\" data-wp-pid=\"28981\" srcset=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-7-Figure-1-New-Project-Wizard-600x418.png 600w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-7-Figure-1-New-Project-Wizard-135x93.png 135w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-7-Figure-1-New-Project-Wizard.png 975w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><figcaption id=\"caption-attachment-28981\" class=\"wp-caption-text\">Figure 1: New Project Wizard<\/figcaption><\/figure>\n<figure id=\"attachment_28982\" aria-describedby=\"caption-attachment-28982\" style=\"width: 600px\" class=\"wp-caption aligncenter\"><img loading=\"lazy\" decoding=\"async\" class=\"size-medium wp-image-28982\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-7-Figure-2-RTL-Project-Selected-600x72.png\" alt=\"\" width=\"600\" height=\"72\" data-wp-pid=\"28982\" srcset=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-7-Figure-2-RTL-Project-Selected-600x72.png 600w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-7-Figure-2-RTL-Project-Selected.png 908w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><figcaption id=\"caption-attachment-28982\" class=\"wp-caption-text\">Figure 2: RTL Project Selected<\/figcaption><\/figure>\n<p>The constraints file provided from Digilent for the <a href=\"https:\/\/digilent.com\/shop\/eclypse-z7-zynq-7000-soc-development-board-with-syzygy-compatible-expansion\/\">Eclypse Z7<\/a> board has been added together with a constraints file I have constructed for the new Zmods. The constraints file is simply the declaration of which I\/Os are connected from the SoC to the Zmod ports.<\/p>\n<figure id=\"attachment_28984\" aria-describedby=\"caption-attachment-28984\" style=\"width: 600px\" class=\"wp-caption aligncenter\"><img loading=\"lazy\" decoding=\"async\" class=\"size-medium wp-image-28984\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-7-Figure-3-Constraints-Files-600x419.png\" alt=\"\" width=\"600\" height=\"419\" data-wp-pid=\"28984\" srcset=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-7-Figure-3-Constraints-Files-600x419.png 600w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-7-Figure-3-Constraints-Files-135x93.png 135w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-7-Figure-3-Constraints-Files.png 980w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><figcaption id=\"caption-attachment-28984\" class=\"wp-caption-text\">Figure 3: Constraints Files<\/figcaption><\/figure>\n<p>Once a new project has been created, a new block design must be added. This is done by clicking on the \u2018Create Block Design\u2019 button on the Vivado \u2018Project Manager\u2019 tab.<\/p>\n<figure id=\"attachment_28985\" aria-describedby=\"caption-attachment-28985\" style=\"width: 344px\" class=\"wp-caption aligncenter\"><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-28985\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-7-Figure-4-Creating-a-Block-Design.png\" alt=\"\" width=\"344\" height=\"233\" data-wp-pid=\"28985\" \/><figcaption id=\"caption-attachment-28985\" class=\"wp-caption-text\">Figure 4: Creating a Block Design<\/figcaption><\/figure>\n<p>Now that the block design has been created, we will need to define the IP catalog. This is the folder where we have saved our custom IP in the previous entry. By clicking the \u2018IP Catalog\u2019 button on the \u2018Project Manager\u2019 tab of Vivado, the IP catalog tab will be opened. Right click on the empty space and click on \u2018Add Repository\u2019, as illustrated in Figure 5.<\/p>\n<figure id=\"attachment_28986\" aria-describedby=\"caption-attachment-28986\" style=\"width: 387px\" class=\"wp-caption aligncenter\"><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-28986\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-7-Figure-5-Adding-an-IP-Repository-in-Vivado.png\" alt=\"\" width=\"387\" height=\"401\" data-wp-pid=\"28986\" \/><figcaption id=\"caption-attachment-28986\" class=\"wp-caption-text\">Figure 5: Adding an IP Repository in Vivado<\/figcaption><\/figure>\n<p>The next step is to navigate to the folder containing the repository and selecting it. Vivado should automatically find the IPs in the repository. And hence from the \u2018add IP\u2019 button in the block design the new IP should be visible.<\/p>\n<figure id=\"attachment_28987\" aria-describedby=\"caption-attachment-28987\" style=\"width: 288px\" class=\"wp-caption aligncenter\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-28987 size-full\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-7-Figure-6-IP-in-Vivado.png\" alt=\"\" width=\"288\" height=\"106\" data-wp-pid=\"28987\" \/><figcaption id=\"caption-attachment-28987\" class=\"wp-caption-text\">Figure 6: IP in Vivado<\/figcaption><\/figure>\n<p>Besides our custom-made IP, we will also need the ZYNQ7 processing system. Right-click on an empty space on the block design and searching for the IP core. We will need to define the output ports which we will be testing on the Zmods. This is done by right-clicking on the block diagram and selecting the \u2018add Port\u2019 option (Figure 7). The output or input ports must match the names defined in the constraints files. The block design should look like Figure 8 below, after clicking on the \u2018Run Connection Automation\u2019 and \u2018Run Block Automation\u2019 buttons on the top side of the block design.<\/p>\n<figure id=\"attachment_28988\" aria-describedby=\"caption-attachment-28988\" style=\"width: 487px\" class=\"wp-caption aligncenter\"><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-28988\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-7-Figure-7-Adding-an-Output-Port.png\" alt=\"\" width=\"487\" height=\"401\" data-wp-pid=\"28988\" \/><figcaption id=\"caption-attachment-28988\" class=\"wp-caption-text\">Figure 7: Adding an Output Port<\/figcaption><\/figure>\n<figure id=\"attachment_28989\" aria-describedby=\"caption-attachment-28989\" style=\"width: 600px\" class=\"wp-caption aligncenter\"><img loading=\"lazy\" decoding=\"async\" class=\"size-medium wp-image-28989\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-7-Figure-8-Block-Design-600x268.png\" alt=\"\" width=\"600\" height=\"268\" data-wp-pid=\"28989\" srcset=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-7-Figure-8-Block-Design-600x268.png 600w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-7-Figure-8-Block-Design-735x330.png 735w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-7-Figure-8-Block-Design.png 739w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><figcaption id=\"caption-attachment-28989\" class=\"wp-caption-text\">Figure 8: Block Design<\/figcaption><\/figure>\n<p>We must now create an HDL wrapper. You can do this is done by right-clicking on the block design file in the \u2018Design Sources\u2019 tab and selecting \u2018Create HDL Wrapper\u2019. Once the HDL wrapper has been created, the project files should look like Figure 10 below.<\/p>\n<figure id=\"attachment_28991\" aria-describedby=\"caption-attachment-28991\" style=\"width: 415px\" class=\"wp-caption aligncenter\"><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-28991\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-7-Figure-9-Adding-an-HDL-Wrapper.png\" alt=\"\" width=\"415\" height=\"296\" data-wp-pid=\"28991\" \/><figcaption id=\"caption-attachment-28991\" class=\"wp-caption-text\">Figure 9: Adding an HDL Wrapper<\/figcaption><\/figure>\n<figure id=\"attachment_28990\" aria-describedby=\"caption-attachment-28990\" style=\"width: 394px\" class=\"wp-caption aligncenter\"><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-28990\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-7-Figure-10-Design-Sources-with-an-HDL-Wrapper.png\" alt=\"\" width=\"394\" height=\"96\" data-wp-pid=\"28990\" \/><figcaption id=\"caption-attachment-28990\" class=\"wp-caption-text\">Figure 10: Design Sources with an HDL Wrapper<\/figcaption><\/figure>\n<p>Once the HDL wrapper has been successfully created, we can now generate our bitstream. The bitstream is the file which will be loaded into the SoC and will also include hardware specification to be used by Vitis to program the processing system. The \u2018Generate Bitstream\u2019 button can be found on the bottom left corner of Vivado.<\/p>\n<figure id=\"attachment_28992\" aria-describedby=\"caption-attachment-28992\" style=\"width: 201px\" class=\"wp-caption aligncenter\"><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-28992\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-7-Figure-11-Generate-Bitstream.png\" alt=\"\" width=\"201\" height=\"111\" data-wp-pid=\"28992\" \/><figcaption id=\"caption-attachment-28992\" class=\"wp-caption-text\">Figure 11: Generate Bitstream<\/figcaption><\/figure>\n<p>Once the design has finished generating the bitstream, the below window should pop up. I generally do not need to open the implemented design so here I suggest choosing cancel. We must now export the hardware so we can develop the processing system code and program the design into the SoC! This is done by going to \u2018File\u2019 -&gt; \u2018Export\u2019 -&gt; \u2018Export Hardware\u2019.<\/p>\n<figure id=\"attachment_28993\" aria-describedby=\"caption-attachment-28993\" style=\"width: 428px\" class=\"wp-caption aligncenter\"><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-28993\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-7-Figure-12-Export-Hardware.png\" alt=\"\" width=\"428\" height=\"491\" data-wp-pid=\"28993\" \/><figcaption id=\"caption-attachment-28993\" class=\"wp-caption-text\">Figure 12: Export Hardware<\/figcaption><\/figure>\n<p>Make sure you select the &#8220;Include Bitstream&#8221; option!<\/p>\n<figure id=\"attachment_28994\" aria-describedby=\"caption-attachment-28994\" style=\"width: 600px\" class=\"wp-caption aligncenter\"><img loading=\"lazy\" decoding=\"async\" class=\"size-medium wp-image-28994\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-7-Figure-13-Select-Include-Bitsream-Option-600x166.png\" alt=\"\" width=\"600\" height=\"166\" data-wp-pid=\"28994\" srcset=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-7-Figure-13-Select-Include-Bitsream-Option-600x166.png 600w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-7-Figure-13-Select-Include-Bitsream-Option.png 764w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><figcaption id=\"caption-attachment-28994\" class=\"wp-caption-text\">Figure 13: Select Include Bitsream Option<\/figcaption><\/figure>\n<p>Once the hardware specification of our design has been exported, the Vivado side of our project is now finished (unless we need to update in the future). In the next entry a Vitis application project based on this exported hardware specification will be created and loaded into the SoC on the Eclypse Z7! The ADP5250 will be used to analyze the resulting outputs from the Eclypse and designed Zmods!<\/p>\n<div class='watch-action'><div class='watch-position align-left'><div class='action-like'><a class='lbg-style6 like-28979 jlk' data-task='like' data-post_id='28979' data-nonce='6d5ef3a62d' rel='nofollow'><img src='https:\/\/digilent.com\/blog\/wp-content\/plugins\/wti-like-post-pro\/images\/pixel.gif' title='Like' \/><span class='lc-28979 lc'>0<\/span><\/a><\/div><div class='action-unlike'><a class='unlbg-style6 unlike-28979 jlk' data-task='unlike' data-post_id='28979' data-nonce='6d5ef3a62d' rel='nofollow'><img src='https:\/\/digilent.com\/blog\/wp-content\/plugins\/wti-like-post-pro\/images\/pixel.gif' title='Unlike' \/><span class='unlc-28979 unlc'>0<\/span><\/a><\/div><\/div> <div class='status-28979 status align-left'>Be the 1st to vote.<\/div><\/div><div class='wti-clear'><\/div>","protected":false},"excerpt":{"rendered":"<p>Editor&#8217;s Note &#8211; In this series, we will take a behind the scenes look at how an engineer tackles a project from beginning to end. What challenges will come up? &hellip; <\/p>\n","protected":false},"author":56,"featured_media":28980,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0,"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[38,4327,35],"tags":[4351,4346,1732,4347],"ppma_author":[4504],"class_list":["post-28979","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-expansion-modules","category-projects","category-fpga","tag-eclypse","tag-engineers-in-the-wild","tag-fpga-design","tag-zmod"],"jetpack_featured_media_url":"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/EngineersInTheWild-Post-7.png","jetpack_sharing_enabled":true,"authors":[{"term_id":4504,"user_id":56,"is_guest":0,"slug":"rdamato","display_name":"Ryan Damato","avatar_url":"https:\/\/secure.gravatar.com\/avatar\/459d8df32d220f6974c7a1e2801026cba7993b5cbebb3cef3d55281388b372b1?s=96&d=mm&r=g","1":"","2":"","3":"","4":"","5":"","6":"","7":"","8":"","9":"","10":""}],"post_mailing_queue_ids":[],"_links":{"self":[{"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/posts\/28979","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/users\/56"}],"replies":[{"embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/comments?post=28979"}],"version-history":[{"count":1,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/posts\/28979\/revisions"}],"predecessor-version":[{"id":29625,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/posts\/28979\/revisions\/29625"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/media\/28980"}],"wp:attachment":[{"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/media?parent=28979"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/categories?post=28979"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/tags?post=28979"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/ppma_author?post=28979"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}