{"id":28965,"date":"2022-03-25T09:13:20","date_gmt":"2022-03-25T16:13:20","guid":{"rendered":"https:\/\/digilent.com\/blog\/?p=28965"},"modified":"2023-02-07T17:23:57","modified_gmt":"2023-02-08T01:23:57","slug":"engineers-in-the-wild-packaging-an-ip-in-vivado","status":"publish","type":"post","link":"https:\/\/digilent.com\/blog\/engineers-in-the-wild-packaging-an-ip-in-vivado\/","title":{"rendered":"Engineers in the Wild: Packaging an IP in Vivado"},"content":{"rendered":"<p><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter size-full wp-image-28971\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/EngineersInTheWild-Post-6.png\" alt=\"\" width=\"580\" height=\"300\" data-wp-pid=\"28971\" \/><\/p>\n<p><em>Editor&#8217;s Note &#8211; In this series, we will take a behind the scenes look at how an engineer tackles a project from beginning to end. What challenges will come up? How can we face problems and come up with solutions? Aside from project completion, what are successes that we can celebrate along the way?<\/em><\/p>\n<ul>\n<li><em><a href=\"https:\/\/digilent.com\/blog\/engineers-in-the-wild-introducing-ryan-damato\/\">Post 1 &#8211; Introducing Ryan<\/a><\/em><\/li>\n<li><em><a href=\"https:\/\/digilent.com\/blog\/engineers-in-the-wild-wireless-radio-frequency-circuit-design-initial-considerations\/\">Post 2 &#8211; Initial Considerations<\/a><\/em><\/li>\n<li><em><a href=\"https:\/\/digilent.com\/blog\/engineers-in-the-wild-designing-a-zmod-peripheral\/\">Post 3 &#8211; Designing a Zmod Peripheral<\/a><\/em><\/li>\n<li><a href=\"https:\/\/digilent.com\/blog\/engineers-in-the-wild-setting-up-syzygy-dna-data\/\"><em>Post 4 &#8211; Setting Up SYZYGY DNA<\/em><\/a><\/li>\n<li><em><a href=\"https:\/\/digilent.com\/blog\/engineers-in-the-wild-writing-syzygy-dna-using-the-adp3450\/\">Post 5 &#8211; Writing SYZYGY DNA Using the ADP3450<\/a><\/em><\/li>\n<\/ul>\n<h2>Packaging an IP in Xilinx&#8217;s Vivado<\/h2>\n<p>In order to check that all connections between the SoC on the Eclypse and our newly designed Zmods, a test project has to be constructed and loaded into the Eclypse Z7. Some IP sources will be needed to provide the necessary functionality. For this project a simple VHDL clock divider is going to be used in order to output square waves of variable desired frequencies on the outputs. As shown in the figure below, a new Vivado project has been opened in my IP repository folder. Figure 2 illustrates the chosen option, \u2018RTL Project\u2019.<\/p>\n<figure id=\"attachment_28966\" aria-describedby=\"caption-attachment-28966\" style=\"width: 600px\" class=\"wp-caption aligncenter\"><img loading=\"lazy\" decoding=\"async\" class=\"size-medium wp-image-28966\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-6-Pic-1-Creating-a-Vivado-Project-600x425.png\" alt=\"\" width=\"600\" height=\"425\" data-wp-pid=\"28966\" srcset=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-6-Pic-1-Creating-a-Vivado-Project-600x425.png 600w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-6-Pic-1-Creating-a-Vivado-Project.png 985w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><figcaption id=\"caption-attachment-28966\" class=\"wp-caption-text\">Figure 1: Creating a Vivado Project<\/figcaption><\/figure>\n<figure id=\"attachment_28967\" aria-describedby=\"caption-attachment-28967\" style=\"width: 600px\" class=\"wp-caption aligncenter\"><img loading=\"lazy\" decoding=\"async\" class=\"size-medium wp-image-28967\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-6-Pic-2-Chosing-Project-Option-in-Vivado-600x69.png\" alt=\"\" width=\"600\" height=\"69\" data-wp-pid=\"28967\" srcset=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-6-Pic-2-Chosing-Project-Option-in-Vivado-600x69.png 600w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-6-Pic-2-Chosing-Project-Option-in-Vivado.png 900w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><figcaption id=\"caption-attachment-28967\" class=\"wp-caption-text\">Figure 2: Choosing Project Option in Vivado<\/figcaption><\/figure>\n<p>A new VHDL file in the project has been created as shown in the figure below.<\/p>\n<figure id=\"attachment_28968\" aria-describedby=\"caption-attachment-28968\" style=\"width: 373px\" class=\"wp-caption aligncenter\"><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-28968\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-6-Pic-3-Create-VHDL-File.png\" alt=\"\" width=\"373\" height=\"287\" data-wp-pid=\"28968\" \/><figcaption id=\"caption-attachment-28968\" class=\"wp-caption-text\">Figure 3: Create a VHDL File<\/figcaption><\/figure>\n<p>When the window to choose your device pops up, the vendor setting defaults to \u2018digilentinc.com\u2019 and the Eclypse Z7 board has been chosen. Make sure you have the<a href=\"https:\/\/github.com\/Digilent\/vivado-boards?_ga=2.248154567.1549992248.1648063143-330803696.1629744359\"> Digilent board files<\/a> installed!<\/p>\n<figure id=\"attachment_28969\" aria-describedby=\"caption-attachment-28969\" style=\"width: 600px\" class=\"wp-caption aligncenter\"><img loading=\"lazy\" decoding=\"async\" class=\"size-medium wp-image-28969\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-6-Pic-4-Digilent-Boards-Files-Eclypse-Z7-Chosen-600x283.png\" alt=\"\" width=\"600\" height=\"283\" data-wp-pid=\"28969\" srcset=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-6-Pic-4-Digilent-Boards-Files-Eclypse-Z7-Chosen-600x283.png 600w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-6-Pic-4-Digilent-Boards-Files-Eclypse-Z7-Chosen.png 936w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><figcaption id=\"caption-attachment-28969\" class=\"wp-caption-text\">Figure 4: Digilent Boards Files, Eclypse Z7 Chosen<\/figcaption><\/figure>\n<p>The VHDL code pasted at the end of this post is the VHDL functionality of a clock divider with one clock input and two clock outputs. After the code has been written in the VHDL file created in the Vivado project, from the \u2018Tools\u2019 menu in Vivado, \u2018Create and package new IP\u2019 option has been chosen. In the pop up window, the \u2018Package Your Current Project\u2019 option has been chosen (Figure 5). This will package our Vivado project into an IP!<\/p>\n<figure id=\"attachment_28970\" aria-describedby=\"caption-attachment-28970\" style=\"width: 600px\" class=\"wp-caption aligncenter\"><img loading=\"lazy\" decoding=\"async\" class=\"size-medium wp-image-28970\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-6-Pic-5-Vivado-Packaging-Options-600x104.png\" alt=\"\" width=\"600\" height=\"104\" data-wp-pid=\"28970\" srcset=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-6-Pic-5-Vivado-Packaging-Options-600x104.png 600w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-6-Pic-5-Vivado-Packaging-Options.png 777w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><figcaption id=\"caption-attachment-28970\" class=\"wp-caption-text\">Figure 5: Vivado Packaging Options<\/figcaption><\/figure>\n<p>After selecting the location for packaging the IP, the window illustrated in Figure 6 should appear on your screen.<\/p>\n<figure id=\"attachment_28972\" aria-describedby=\"caption-attachment-28972\" style=\"width: 600px\" class=\"wp-caption aligncenter\"><img loading=\"lazy\" decoding=\"async\" class=\"size-medium wp-image-28972\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-6-Pic-6-Editing-Customization-Paramters-600x573.png\" alt=\"\" width=\"600\" height=\"573\" data-wp-pid=\"28972\" srcset=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-6-Pic-6-Editing-Customization-Paramters-600x573.png 600w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-6-Pic-6-Editing-Customization-Paramters.png 639w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><figcaption id=\"caption-attachment-28972\" class=\"wp-caption-text\">Figure 6: Editing Customization Parameters<\/figcaption><\/figure>\n<p>From the \u2018Customization Parameters\u2019 tab of the IP Packager, the parameters can be edited. In this case I have put a range value to these parameters as illustrated in the figure below.<\/p>\n<figure id=\"attachment_28973\" aria-describedby=\"caption-attachment-28973\" style=\"width: 600px\" class=\"wp-caption aligncenter\"><img loading=\"lazy\" decoding=\"async\" class=\"size-medium wp-image-28973\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-6-Pic-7-IP-Packager-Settings-600x271.png\" alt=\"\" width=\"600\" height=\"271\" data-wp-pid=\"28973\" srcset=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-6-Pic-7-IP-Packager-Settings-600x271.png 600w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-6-Pic-7-IP-Packager-Settings-1024x463.png 1024w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-6-Pic-7-IP-Packager-Settings.png 1483w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><figcaption id=\"caption-attachment-28973\" class=\"wp-caption-text\">Figure 7: IP Packager Settings<\/figcaption><\/figure>\n<p>After all has been set, the \u2018Package IP\u2019 button has been pressed (Figure 8).<\/p>\n<figure id=\"attachment_28974\" aria-describedby=\"caption-attachment-28974\" style=\"width: 600px\" class=\"wp-caption aligncenter\"><img loading=\"lazy\" decoding=\"async\" class=\"size-medium wp-image-28974\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-6-Pic-8-Package-IP-600x241.png\" alt=\"\" width=\"600\" height=\"241\" data-wp-pid=\"28974\" srcset=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-6-Pic-8-Package-IP-600x241.png 600w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-6-Pic-8-Package-IP.png 788w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><figcaption id=\"caption-attachment-28974\" class=\"wp-caption-text\">Figure 8: Package IP<\/figcaption><\/figure>\n<p>Figures 9 and 10 show how the packaged IP looks in a separate project in Vivado.<\/p>\n<figure id=\"attachment_28975\" aria-describedby=\"caption-attachment-28975\" style=\"width: 284px\" class=\"wp-caption aligncenter\"><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-28975\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-6-Pic-9-Packaged-IP.png\" alt=\"\" width=\"284\" height=\"212\" data-wp-pid=\"28975\" \/><figcaption id=\"caption-attachment-28975\" class=\"wp-caption-text\">Figure 9: Packaged IP<\/figcaption><\/figure>\n<figure id=\"attachment_28976\" aria-describedby=\"caption-attachment-28976\" style=\"width: 600px\" class=\"wp-caption aligncenter\"><img loading=\"lazy\" decoding=\"async\" class=\"size-medium wp-image-28976\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-6-Pic-10-IP-Variable-Settings-600x487.png\" alt=\"\" width=\"600\" height=\"487\" data-wp-pid=\"28976\" srcset=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-6-Pic-10-IP-Variable-Settings-600x487.png 600w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/Post-6-Pic-10-IP-Variable-Settings.png 778w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><figcaption id=\"caption-attachment-28976\" class=\"wp-caption-text\">Figure 10: IP Variable Settings<\/figcaption><\/figure>\n<p>Now the IP has been successfully packaged!<\/p>\n<p>The VHDL divider code basically works by counting the times a positive edge is present on the input clock. When the counters reach the value set by the user, the output clock logic state is inverted. This provides a division of the input clock frequency on the output clock.<\/p>\n<blockquote><p><strong>library<\/strong> IEEE<strong>;<\/strong><\/p>\n<p><strong>use<\/strong> IEEE<strong>.<\/strong>STD_LOGIC_1164<strong>.<\/strong><strong>ALL<\/strong><strong>;<\/strong><\/p>\n<p><strong>use<\/strong> IEEE<strong>.<\/strong>numeric_std<strong>.<\/strong><strong>ALL<\/strong><strong>;<\/strong><\/p>\n<p>&#8212; Uncomment the following library declaration if using<\/p>\n<p>&#8212; arithmetic functions with Signed or Unsigned values<\/p>\n<p>&#8211;use IEEE.NUMERIC_STD.ALL;<\/p>\n<p>&#8212; Uncomment the following library declaration if instantiating<\/p>\n<p>&#8212; any Xilinx leaf cells in this code.<\/p>\n<p>&#8211;library UNISIM;<\/p>\n<p>&#8211;use UNISIM.VComponents.all;<\/p>\n<p><strong>entity<\/strong> Divider_Variable <strong>is<\/strong><\/p>\n<p><strong>Generic<\/strong><strong>(<\/strong><\/p>\n<p>Counter_1<strong>:<\/strong> INTEGER <strong>:=<\/strong> 5000<strong>;<\/strong><\/p>\n<p>Counter_2<strong>:<\/strong> INTEGER <strong>:=<\/strong> 10000<\/p>\n<p><strong>);<\/strong><\/p>\n<p><strong>Port<\/strong> <strong>(<\/strong><\/p>\n<p>Clock_In<strong>:<\/strong> <strong>in<\/strong> std_logic<strong>;<\/strong><\/p>\n<p>Clock_Out_1<strong>:<\/strong> <strong>out<\/strong> std_logic<strong>;<\/strong><\/p>\n<p>Clock_Out_2<strong>:<\/strong> <strong>out<\/strong> std_logic<\/p>\n<p><strong>);<\/strong><\/p>\n<p><strong>end<\/strong> Divider_Variable<strong>;<\/strong><\/p>\n<p><strong>architecture<\/strong> Behavioral <strong>of<\/strong> Divider_Variable <strong>is<\/strong><\/p>\n<p><strong>signal<\/strong> count_1<strong>,<\/strong> count_2<strong>:<\/strong> integer<strong>:=<\/strong>1<strong>;<\/strong><\/p>\n<p><strong>signal<\/strong> tmp_1<strong>,<\/strong> tmp_2 <strong>:<\/strong> std_logic <strong>:=<\/strong> &#8216;0&#8217;<strong>;<\/strong><\/p>\n<p><strong>begin<\/strong><\/p>\n<p><strong>process<\/strong><strong>(<\/strong>Clock_In<strong>)<\/strong><\/p>\n<p><strong>begin<\/strong><\/p>\n<p><strong>if<\/strong><strong>(<\/strong>Clock_In&#8217;<strong>event<\/strong> and Clock_In<strong>=<\/strong>&#8216;1&#8217;<strong>)<\/strong> <strong>then<\/strong><\/p>\n<p>count_1 <strong>&lt;=<\/strong>count_1<strong>+<\/strong>1<strong>;<\/strong><\/p>\n<p><strong>if<\/strong> <strong>(<\/strong>count_1 <strong>=<\/strong> Counter_1<strong>)<\/strong> <strong>then<\/strong><\/p>\n<p>tmp_1 <strong>&lt;=<\/strong> NOT tmp_1<strong>;<\/strong><\/p>\n<p>count_1 <strong>&lt;=<\/strong> 1<strong>;<\/strong><\/p>\n<p><strong>end<\/strong> <strong>if<\/strong><strong>;<\/strong><\/p>\n<p><strong>end<\/strong> <strong>if<\/strong><strong>;<\/strong><\/p>\n<p>Clock_Out_1 <strong>&lt;=<\/strong> tmp_1<strong>;<\/strong><\/p>\n<p><strong>end<\/strong> <strong>process<\/strong><strong>;<\/strong><\/p>\n<p><strong>process<\/strong><strong>(<\/strong>Clock_In<strong>)<\/strong><\/p>\n<p><strong>begin<\/strong><\/p>\n<p><strong>if<\/strong><strong>(<\/strong>Clock_In&#8217;<strong>event<\/strong> and Clock_In<strong>=<\/strong>&#8216;1&#8217;<strong>)<\/strong> <strong>then<\/strong><\/p>\n<p>count_2 <strong>&lt;=<\/strong>count_2<strong>+<\/strong>1<strong>;<\/strong><\/p>\n<p><strong>if<\/strong> <strong>(<\/strong>count_2 <strong>=<\/strong> Counter_2<strong>)<\/strong> <strong>then<\/strong><\/p>\n<p>tmp_2 <strong>&lt;=<\/strong> NOT tmp_2<strong>;<\/strong><\/p>\n<p>count_2 <strong>&lt;=<\/strong> 1<strong>;<\/strong><\/p>\n<p><strong>end<\/strong> <strong>if<\/strong><strong>;<\/strong><\/p>\n<p><strong>end<\/strong> <strong>if<\/strong><strong>;<\/strong><\/p>\n<p>Clock_Out_2 <strong>&lt;=<\/strong> tmp_2<strong>;<\/strong><\/p>\n<p><strong>end<\/strong> <strong>process<\/strong><strong>;<\/strong><\/p>\n<p><strong>end<\/strong> Behavioral<strong>;<\/strong><\/p>\n<p>&nbsp;<\/p><\/blockquote>\n<p>In the next entry, we will discuss in detail the project which will be used to test the I\/Os on the newly designed Zmods.<\/p>\n<div class='watch-action'><div class='watch-position align-left'><div class='action-like'><a class='lbg-style6 like-28965 jlk' data-task='like' data-post_id='28965' data-nonce='ac068a413b' rel='nofollow'><img src='https:\/\/digilent.com\/blog\/wp-content\/plugins\/wti-like-post-pro\/images\/pixel.gif' title='Like' \/><span class='lc-28965 lc'>0<\/span><\/a><\/div><div class='action-unlike'><a class='unlbg-style6 unlike-28965 jlk' data-task='unlike' data-post_id='28965' data-nonce='ac068a413b' rel='nofollow'><img src='https:\/\/digilent.com\/blog\/wp-content\/plugins\/wti-like-post-pro\/images\/pixel.gif' title='Unlike' \/><span class='unlc-28965 unlc'>0<\/span><\/a><\/div><\/div> <div class='status-28965 status align-left'>Be the 1st to vote.<\/div><\/div><div class='wti-clear'><\/div>","protected":false},"excerpt":{"rendered":"<p>Editor&#8217;s Note &#8211; In this series, we will take a behind the scenes look at how an engineer tackles a project from beginning to end. What challenges will come up? &hellip; <\/p>\n","protected":false},"author":56,"featured_media":28971,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0,"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[38,4327,35],"tags":[4351,4346,1732],"ppma_author":[4504],"class_list":["post-28965","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-expansion-modules","category-projects","category-fpga","tag-eclypse","tag-engineers-in-the-wild","tag-fpga-design"],"jetpack_featured_media_url":"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2022\/03\/EngineersInTheWild-Post-6.png","jetpack_sharing_enabled":true,"authors":[{"term_id":4504,"user_id":56,"is_guest":0,"slug":"rdamato","display_name":"Ryan Damato","avatar_url":"https:\/\/secure.gravatar.com\/avatar\/459d8df32d220f6974c7a1e2801026cba7993b5cbebb3cef3d55281388b372b1?s=96&d=mm&r=g","1":"","2":"","3":"","4":"","5":"","6":"","7":"","8":"","9":"","10":""}],"post_mailing_queue_ids":[],"_links":{"self":[{"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/posts\/28965","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/users\/56"}],"replies":[{"embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/comments?post=28965"}],"version-history":[{"count":1,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/posts\/28965\/revisions"}],"predecessor-version":[{"id":29624,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/posts\/28965\/revisions\/29624"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/media\/28971"}],"wp:attachment":[{"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/media?parent=28965"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/categories?post=28965"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/tags?post=28965"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/ppma_author?post=28965"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}