{"id":27749,"date":"2020-02-06T11:06:10","date_gmt":"2020-02-06T19:06:10","guid":{"rendered":"https:\/\/blog.digilentinc.com\/?p=27749"},"modified":"2020-12-21T11:17:02","modified_gmt":"2020-12-21T19:17:02","slug":"six-reasons-you-should-consider-fpgas-over-asics-or-cpu-gpus","status":"publish","type":"post","link":"https:\/\/digilent.com\/blog\/six-reasons-you-should-consider-fpgas-over-asics-or-cpu-gpus\/","title":{"rendered":"Six Reasons You Should Consider FPGAs Over ASICs or CPU\/GPUs\u00a0"},"content":{"rendered":"<p><span data-contrast=\"auto\">In this blog post, we\u2019ll be focusing on why\u00a0<\/span><span data-contrast=\"auto\">FPGAs hit the sweet spot\u00a0<\/span><span data-contrast=\"auto\">for processing power<\/span><span data-contrast=\"auto\">.<\/span><span data-contrast=\"auto\">\u00a0<\/span><span data-contrast=\"auto\">Before we dive too deeply into this conversation, let&#8217;s address the \u201celephant in the room\u201d &#8211;\u00a0<\/span><span data-contrast=\"auto\">everything exists for a reason, even ASICs<\/span><span data-contrast=\"auto\">\u00a0(<\/span><span data-contrast=\"auto\">A<\/span><span data-contrast=\"auto\">pplication\u00a0<\/span><span data-contrast=\"auto\">S<\/span><span data-contrast=\"auto\">pecific\u00a0<\/span><span data-contrast=\"auto\">I<\/span><span data-contrast=\"auto\">ntegrated\u00a0<\/span><span data-contrast=\"auto\">C<\/span><span data-contrast=\"auto\">ircuit)<\/span><span data-contrast=\"auto\">, CPUs (<\/span><span data-contrast=\"auto\">C<\/span><span data-contrast=\"auto\">entral Processing\u00a0<\/span><span data-contrast=\"auto\">U<\/span><span data-contrast=\"auto\">nit), and GPUs (<\/span><span data-contrast=\"auto\">G<\/span><span data-contrast=\"auto\">raphics\u00a0<\/span><span data-contrast=\"auto\">P<\/span><span data-contrast=\"auto\">rocessing\u00a0<\/span><span data-contrast=\"auto\">U<\/span><span data-contrast=\"auto\">nit). ASIC<\/span><span data-contrast=\"auto\">s provide incredible\u00a0<\/span><span data-contrast=\"auto\">p<\/span><span data-contrast=\"auto\">erformance<\/span><span data-contrast=\"auto\">\u00a0per watt<\/span><span data-contrast=\"auto\">, and are thus very efficient, but they are also much more challenging to\u00a0<\/span><span data-contrast=\"auto\">design<\/span><span data-contrast=\"auto\">\u00a0<\/span><span data-contrast=\"auto\">and\u00a0<\/span><span data-contrast=\"auto\">are more pricey<\/span><span data-contrast=\"auto\">\u00a0<\/span><span data-contrast=\"auto\">than\u00a0<\/span><span data-contrast=\"auto\">using\u00a0<\/span><span data-contrast=\"auto\">an FPGA<\/span><span data-contrast=\"auto\">\u00a0(<\/span><span data-contrast=\"auto\">F<\/span><span data-contrast=\"auto\">ield\u00a0<\/span><span data-contrast=\"auto\">P<\/span><span data-contrast=\"auto\">rogrammable\u00a0<\/span><span data-contrast=\"auto\">G<\/span><span data-contrast=\"auto\">ate\u00a0<\/span><span data-contrast=\"auto\">A<\/span><span data-contrast=\"auto\">rray<\/span><span data-contrast=\"auto\">). On the other end of the spectrum, CPUs\/GPUs have the edge\u00a0<\/span><span data-contrast=\"auto\">in<\/span><span data-contrast=\"auto\">\u00a0ease of programming and design but\u00a0<\/span><span data-contrast=\"auto\">lack the efficiency of the others.<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:259}\">\u00a0<\/span><\/p>\n<p><span data-contrast=\"auto\">Without any further ado, let\u2019s get to the list:<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:259}\">\u00a0<\/span><\/p>\n<p><span data-contrast=\"auto\">1)\u00a0<\/span><b><span data-contrast=\"auto\">FPGAs are\u00a0<\/span><\/b><b><span data-contrast=\"auto\">Re<\/span><\/b><b><span data-contrast=\"auto\">configur<\/span><\/b><b><span data-contrast=\"auto\">able<\/span><\/b><span data-contrast=\"auto\">\u00a0&#8211;\u00a0<\/span><span data-contrast=\"auto\">The configurability of your average FPGA leaves ASICs in the dust.\u00a0<\/span><span data-contrast=\"auto\">In addition to the hard\/soft IP cores\u00a0<\/span><span data-contrast=\"auto\">(an example: Arm Core on our\u00a0<\/span><span data-contrast=\"auto\">Arty Z7)\u00a0<\/span><span data-contrast=\"auto\">that are configured for a specific application, the real value lies in being able to reconfigure\u00a0<\/span><span data-contrast=\"auto\">(and reconfigure again)\u00a0<\/span><i><span data-contrast=\"auto\">after<\/span><\/i><span data-contrast=\"auto\">\u00a0installation \u2013 something that\u00a0<\/span><span data-contrast=\"auto\">ASICs just can\u2019t do<\/span><span data-contrast=\"auto\">.<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:259}\">\u00a0<\/span><\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-27751\" src=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2020\/02\/fpga-schematic.png\" alt=\"fpga schematic\" width=\"1222\" height=\"455\" data-wp-pid=\"27751\" srcset=\"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2020\/02\/fpga-schematic.png 1222w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2020\/02\/fpga-schematic-600x223.png 600w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2020\/02\/fpga-schematic-1024x381.png 1024w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2020\/02\/fpga-schematic-768x286.png 768w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2020\/02\/fpga-schematic-800x298.png 800w, https:\/\/digilent.com\/blog\/wp-content\/uploads\/2020\/02\/fpga-schematic-1200x447.png 1200w\" sizes=\"auto, (max-width: 1222px) 100vw, 1222px\" \/><\/p>\n<p>&nbsp;<\/p>\n<p><span data-contrast=\"auto\">2)\u00a0<\/span><b><span data-contrast=\"auto\">FPGAs Work\u00a0<\/span><\/b><b><span data-contrast=\"auto\">i<\/span><\/b><b><span data-contrast=\"auto\">n Parallel \u2013\u00a0<\/span><\/b><span data-contrast=\"auto\">One of the benefits of FPGAs that make them such a good tool for working\u00a0<\/span><span data-contrast=\"auto\">with measurement systems and other edge computing applications that require\u00a0<\/span><span data-contrast=\"auto\">the processing of a large amount of data<\/span><span data-contrast=\"auto\">\u00a0like embedded vision is that they\u00a0<\/span><span data-contrast=\"auto\">are able to<\/span><span data-contrast=\"auto\">\u00a0process in parallel.\u00a0<\/span><span data-contrast=\"auto\">CPUs\/GPUs work sequentially, processing one piece at a time, but with a well-configured FPGA you\u2019ll be able to<\/span><span data-contrast=\"auto\">\u00a0simultaneously\u00a0<\/span><span data-contrast=\"auto\">intake and process the next ba<\/span><span data-contrast=\"auto\">tch of information before the first\u00a0<\/span><span data-contrast=\"auto\">batch<\/span><span data-contrast=\"auto\">\u00a0is done<\/span><span data-contrast=\"auto\">, giving a low latency.\u00a0<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:259}\">\u00a0<\/span><\/p>\n<p><span data-contrast=\"auto\">3)\u00a0<\/span><b><span data-contrast=\"auto\">FPGAS Perform Time-Critical Processing<\/span><\/b><span data-contrast=\"auto\">\u00a0&#8211; With the\u00a0<\/span><span data-contrast=\"auto\">aforementioned low<\/span><span data-contrast=\"auto\">\u00a0<\/span><span data-contrast=\"auto\">latency,\u00a0<\/span><span data-contrast=\"auto\">engineers and developers are able to use FPGAs for applications that require\u00a0<\/span><span data-contrast=\"auto\">very time-critical calculations; like software-defined radio, medical devices, and mil-aero systems.\u00a0<\/span><span data-contrast=\"auto\">When\u00a0<\/span><span data-contrast=\"auto\">you don\u2019t have to wait as long on\u00a0<\/span><span data-contrast=\"auto\">the processor\u00a0<\/span><span data-contrast=\"auto\">t<\/span><span data-contrast=\"auto\">o<\/span><span data-contrast=\"auto\">\u00a0complete a calculation<\/span><span data-contrast=\"auto\">,\u00a0<\/span><span data-contrast=\"auto\">the output can be much more accurate.<\/span><span data-contrast=\"auto\">\u00a0ASICs have even less latency, but again, they are only for a single specific application<\/span><span data-contrast=\"auto\">. For prototyping and design, FPGA is the more forgiving choice.\u00a0<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:259}\">\u00a0<\/span><\/p>\n<p><span data-contrast=\"auto\">4)\u00a0<\/span><b><span data-contrast=\"auto\">FPGAs Have Optimal Performance per Watt<\/span><\/b><b><span data-contrast=\"auto\">\u00a0\u2013\u00a0<\/span><\/b><span data-contrast=\"auto\">When compared with a\u00a0<\/span><span data-contrast=\"auto\">CPU or GPU, you will be getting high<\/span><span data-contrast=\"auto\">er<\/span><span data-contrast=\"auto\">\u00a0performance per watt (though it is closer when using floating point arithmetic)\u00a0<\/span><span data-contrast=\"auto\">with an FPGA.\u00a0<\/span><span data-contrast=\"auto\">This low power consumption can be nearly 3 to 4 times less than that of a GPU. The operating cost of an ASIC is far and away the best, but the high initial cost (sometimes in the millions) does a lot to offset that.<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:259}\">\u00a0<\/span><\/p>\n<p><span data-contrast=\"auto\">5) <\/span><b><span data-contrast=\"auto\">No OS Overhead \u2013\u00a0<\/span><\/b><span data-contrast=\"auto\">If the latency and computational power of a CPU\/<\/span><span data-contrast=\"auto\">GPU would be comparable to an FPGA, the inside track i<\/span><span data-contrast=\"auto\">s<\/span><span data-contrast=\"auto\">\u00a0lost by the necessity of running an operating system.\u00a0<\/span><span data-contrast=\"auto\">The OS brings down the\u00a0<\/span><span data-contrast=\"auto\">processing cost efficiency, as resources need to be dedicated to it, increasing the power used and decreasing the compute power.<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:259}\">\u00a0<\/span><\/p>\n<p><span data-contrast=\"auto\">6<\/span><span data-contrast=\"auto\">)\u00a0<\/span><b><span data-contrast=\"auto\">FPGAs are Essentially Blank Canvases<\/span><\/b><b><span data-contrast=\"auto\">\u00a0\u2013\u00a0<\/span><\/b><span data-contrast=\"auto\">While ASICs need to have their functionality\u00a0<\/span><i><span data-contrast=\"auto\">before<\/span><\/i><span data-contrast=\"auto\">\u00a0manufacturing and CPUs\/GPUs\u00a0<\/span><span data-contrast=\"auto\">are optimized for a narrow set of applications<\/span><span data-contrast=\"auto\">, an FPGA\u2019s blueprint is\u00a0<\/span><span data-contrast=\"auto\">almost completely\u00a0<\/span><span data-contrast=\"auto\">user<\/span><span data-contrast=\"auto\">\u00a0<\/span><span data-contrast=\"auto\">defined.\u00a0<\/span><span data-contrast=\"auto\">With the right\u00a0<\/span><span data-contrast=\"auto\">knowledge of HDLs (<\/span><span data-contrast=\"auto\">H<\/span><span data-contrast=\"auto\">ardware\u00a0<\/span><span data-contrast=\"auto\">D<\/span><span data-contrast=\"auto\">esign\u00a0<\/span><span data-contrast=\"auto\">L<\/span><span data-contrast=\"auto\">anguage), an engineer can configure the FPGA f<\/span><span data-contrast=\"auto\">abric to tackle any function, and in a lot of cases, multiple function<\/span><span data-contrast=\"auto\">s<\/span><span data-contrast=\"auto\">. In addition,\u00a0<\/span><span data-contrast=\"auto\">FPGA<\/span><span data-contrast=\"auto\">s<\/span><span data-contrast=\"auto\">\u00a0ha<\/span><span data-contrast=\"auto\">ve<\/span><span data-contrast=\"auto\">\u00a0a huge interface\u00a0<\/span><span data-contrast=\"auto\">flexibility that\u00a0<\/span><span data-contrast=\"auto\">has recently been advanced even more with the rise\u00a0<\/span><span data-contrast=\"auto\">in popularity of SoCs<\/span><span data-contrast=\"auto\">\u00a0<\/span><span data-contrast=\"auto\">(S<\/span><span data-contrast=\"auto\">ystem\u00a0<\/span><span data-contrast=\"auto\">O<\/span><span data-contrast=\"auto\">n<\/span><span data-contrast=\"auto\">\u00a0<\/span><span data-contrast=\"auto\">C<\/span><span data-contrast=\"auto\">hip<\/span><span data-contrast=\"auto\">; Xilinx\u2019s Zynq 7000 SoC can be found on our\u00a0<\/span><span data-contrast=\"auto\">ZedBoard<\/span><span data-contrast=\"auto\">)<\/span><span data-contrast=\"auto\">,<\/span><span data-contrast=\"auto\">\u00a0which<\/span><span data-contrast=\"auto\">\u00a0<\/span><span data-contrast=\"auto\">actually<\/span><span data-contrast=\"auto\">\u00a0include<\/span><span data-contrast=\"auto\">\u00a0a<\/span><span data-contrast=\"auto\">\u00a0CPU<\/span><span data-contrast=\"auto\">\u00a0alongside the FPGA.<\/span><span data-contrast=\"auto\">\u00a0<\/span><span data-contrast=\"auto\">\u00a0<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335551550&quot;:6,&quot;335551620&quot;:6,&quot;335559739&quot;:160,&quot;335559740&quot;:259}\">\u00a0<\/span><\/p>\n<p><span data-contrast=\"auto\">So, yes, there are applications that might be better suited for an ASIC, a CPU, or a GPU, but\u00a0<\/span><span data-contrast=\"auto\">for engineers that are fluent in HDLs, the FPGA hits the mark for price, processing power, and configurability. For those that\u00a0<\/span><span data-contrast=\"auto\">are more versed in languages like C, Java, and Python? Keep an eye on our new\u00a0<\/span><a href=\"https:\/\/digilent.com\/blog\/fpgas-just-got-easier\/\"><span data-contrast=\"auto\">Eclypse<\/span><\/a><span data-contrast=\"auto\"><a href=\"https:\/\/digilent.com\/blog\/fpgas-just-got-easier\/\">\u00a0Z7<\/a>, which\u00a0<\/span><span data-contrast=\"auto\">has high level API that\u00a0<\/span><span data-contrast=\"auto\">will allow\u00a0<\/span><span data-contrast=\"auto\">for\u00a0<\/span><span data-contrast=\"auto\">an easier interaction between FPGAs and\u00a0<\/span><span data-contrast=\"auto\">software languages (currently C and C++ are supported, with more coming later).\u00a0<\/span><span data-ccp-props=\"{&quot;201341983&quot;:0,&quot;335551550&quot;:6,&quot;335551620&quot;:6,&quot;335559739&quot;:160,&quot;335559740&quot;:259}\">\u00a0<\/span><\/p>\n<div class='watch-action'><div class='watch-position align-left'><div class='action-like'><a class='lbg-style6 like-27749 jlk' data-task='like' data-post_id='27749' data-nonce='d8c4d58d14' rel='nofollow'><img src='https:\/\/digilent.com\/blog\/wp-content\/plugins\/wti-like-post-pro\/images\/pixel.gif' title='Like' \/><span class='lc-27749 lc'>+11<\/span><\/a><\/div><div class='action-unlike'><a class='unlbg-style6 unlike-27749 jlk' data-task='unlike' data-post_id='27749' data-nonce='d8c4d58d14' rel='nofollow'><img src='https:\/\/digilent.com\/blog\/wp-content\/plugins\/wti-like-post-pro\/images\/pixel.gif' title='Unlike' \/><span class='unlc-27749 unlc'>0<\/span><\/a><\/div><\/div> <div class='status-27749 status align-left'><\/div><\/div><div class='wti-clear'><\/div>","protected":false},"excerpt":{"rendered":"<p>Is an FPGA the right tool for you? Dive into six ways that will help you discern if an FPGA is the way to go.<\/p>\n","protected":false},"author":50,"featured_media":27900,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0,"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[4267,35,1563],"tags":[],"ppma_author":[4502],"class_list":["post-27749","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-featured","category-fpga","category-guide"],"jetpack_featured_media_url":"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2020\/02\/2020-FPGAsale.png","jetpack_sharing_enabled":true,"authors":[{"term_id":4502,"user_id":50,"is_guest":0,"slug":"davidh","display_name":"David Horn","avatar_url":"https:\/\/secure.gravatar.com\/avatar\/917c337136844f075c76fcf4a0c3b94aa8c225366009ebf63c08fcb9ce6d0e52?s=96&d=mm&r=g","1":"","2":"","3":"","4":"","5":"","6":"","7":"","8":"","9":"","10":""}],"post_mailing_queue_ids":[],"_links":{"self":[{"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/posts\/27749","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/users\/50"}],"replies":[{"embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/comments?post=27749"}],"version-history":[{"count":0,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/posts\/27749\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/media\/27900"}],"wp:attachment":[{"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/media?parent=27749"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/categories?post=27749"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/tags?post=27749"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/ppma_author?post=27749"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}