{"id":25130,"date":"2018-07-20T09:00:24","date_gmt":"2018-07-20T16:00:24","guid":{"rendered":"https:\/\/blog.digilentinc.com\/?p=25130"},"modified":"2023-04-27T13:27:13","modified_gmt":"2023-04-27T20:27:13","slug":"fpga-for-beginners-glossary-and-setup","status":"publish","type":"post","link":"https:\/\/digilent.com\/blog\/fpga-for-beginners-glossary-and-setup\/","title":{"rendered":"FPGA for Beginners: Glossary and Setup"},"content":{"rendered":"

The purpose of this series is to provide an entry point to navigate the world of FPGA boards<\/a> and SoC boards<\/a>. Admittedly, there are a decent number of resources on the topic of FPGA already available online, but the goal of this series is to provide a roadmap for the reader to navigate the current FPGA landscape. This will include discussion of FPGA theory, when\/why one might use FPGA, links to existing resources, and common mistakes and questions one might have when embarking on this learning process. However, we will also supply this discussion with technical discourse and example projects from the book Digital System Design with FPGA by\u00a0Cem \u00dcnsalan and Bora Tar\u2019s.<\/a><\/p>\n

The structure of the series will follow the main stages of an absolute beginner getting started with FPGA, and is applicable whether you are enrolled in class or studying on your own.<\/p>\n

There are a lot of things to consider when getting started with any new hardware platform, and it can be very overwhelming figuring out where to begin. You will need to understand the hardware, how to interface with the hardware, how to make the hardware interface with the outside world, and what tools and knowledge to use to actually do<\/em> any of this. To begin tackling this challenge, we will provide a brief background on what exactly an FPGA is, then define some terms that you will encounter in each stage of the development process.<\/p>\n

The Modern FPGA Landscape<\/strong><\/h2>\n

The first commercially viable field-programmable<\/a>\u00a0gate array<\/a> was invented by Xilinx co-founders\u00a0Ross Freeman<\/a>\u00a0and\u00a0Bernard Vonderschmitt<\/a>\u00a0with their first board in 1985\u00a0\u2013 the XC2064. Since then, Altera (now Intel) and Xilinx continued to grow unchallenged from 1985 to the mid-1990s when competitors began to impose on the market. The 1990\u2019s were a period of rapid FPGA growth both in circuit sophistication and volume of production, and by the end of the decade, FPGA was finding its way into consumer markets.\u00a0 For more on the timeline, check out this post.<\/a><\/p>\n

Today the FPGA market is still dominated by these two major companies- In 2016, they controlled nearly 90 percent of the market. Users choice between the two is largely determined by familiarity with toolsets, however for the purposes of this series we will be using Xilinx [chips]and tools.<\/p>\n

Today, FPGA\u2019s have become affordable enough to gain prevalence in consumer markets. However, due to the complexity of the hardware and design process, it can be intimidating to learn without the direction and resources provided by a formal class. One good place to start when tackling this topic, is to get familiar with the vocabulary used to describe parts of the design process and the hardware itself.<\/p>\n

You might have already encountered some terms and concepts that are often thrown around, such as \u201cdigital Logic, Vivado, bitstream\u201d and so forth. There is a good amount of vocabulary that comes with learning FPGA, but to get us started we have taken some of the more common FPGA terms you might hear, and assembled definitions in our glossary below. (The majority of these definitions are taken from their respective Wikipedia pages or are linked to their original source).<\/p>\n

Glossary of Terms<\/strong><\/h2>\n

FPGA definition:<\/strong> FPGA, meaning A field-programmable gate array, is an integrated circuit<\/a>\u00a0designed to be configured by a customer or a designer after manufacturing\u00a0\u2013 hence “field-programmable<\/a>“. The FPGA configuration is generally specified using a\u00a0hardware description language<\/a>\u00a0(HDL), similar to that used for an\u00a0application-specific integrated circuit<\/a>\u00a0(ASIC). They consist of a collection of logic cells called lookup tables (LUTs) surrounded by an interconnect fabric. The LUTs and fabric<\/a> are programmable, providing a flexible system that can implement almost any digital algorithm.<\/p>\n

Digital logic<\/strong>: Digital logic<\/a>\u00a0is the underlying\u00a0logic<\/em>\u00a0system that drives electronic circuit board design.\u00a0Digital logic\u00a0is the manipulation of binary values through printed circuit board technology that uses circuits and\u00a0logic<\/em>\u00a0gates to construct the implementation of computer operations. It is the fundamental concept underpinning all modern computer systems.<\/p>\n

Digital System:<\/strong> The system you are trying to design. FPGA can be used as a generic platform to implement a digital system on. An FPGA is itself a digital electronic system composed of basic building blocks.<\/p>\n

Design idea<\/strong>: The usage case or application you are designing your system for.<\/p>\n

FPGA HDL definition:<\/strong> (H<\/strong>ardware\u00a0D<\/strong>escription\u00a0L<\/strong>anguage). The two most popular HDLs are Verilog and VHDL<\/p>\n

Verilog:<\/strong> Verilog, standardized as\u00a0IEEE 1364, is a\u00a0hardware description language<\/a>\u00a0(HDL) used to model\u00a0electronic systems<\/a>. It is most commonly used in the\u00a0design and verification<\/a>\u00a0of\u00a0digital circuits<\/a>\u00a0at the\u00a0register-transfer level<\/a>\u00a0of\u00a0abstraction<\/a>. It is also used in the verification of\u00a0analog circuits<\/a>\u00a0and\u00a0mixed-signal circuits<\/a>, as well as in the design of\u00a0genetic circuits<\/a><\/p>\n

VHDL:<\/strong> VHDL\u00a0(VHSIC<\/a>\u00a0Hardware Description Language) is a\u00a0hardware description language<\/a>\u00a0used in\u00a0electronic design automation<\/a>\u00a0to describe\u00a0digital<\/a>\u00a0and\u00a0mixed-signal<\/a>\u00a0systems such as\u00a0field-programmable gate arrays<\/a>\u00a0and\u00a0integrated circuits<\/a>. VHDL can also be used as a general purpose\u00a0parallel programming language<\/a>.<\/p>\n

Vivado:<\/strong> Vivado Design Suite\u00a0is a software suite produced by\u00a0Xilinx<\/a>\u00a0for synthesis and analysis of\u00a0HDL<\/a>\u00a0designs, superseding\u00a0Xilinx ISE<\/a>\u00a0with additional features for\u00a0system on a chip<\/a>\u00a0development and\u00a0high-level synthesis<\/a>.[3]<\/a>[4]<\/a>[5]<\/a><\/sup>[6]<\/sup> Vivado represents a ground-up rewrite and re-thinking of the entire design flow (compared to ISE), and has been described by reviewers as “well conceived, tightly integrated, blazing fast, scalable, maintainable, and intuitive”.<\/p>\n

FPGA RTL definition:<\/strong> In digital circuit design, register-transfer level (RTL<\/a>) is a design abstraction which models a synchronous digital circuit in terms of the flow of digital signals (data) between hardware registers, and the logical operations performed on those signals.<\/p>\n

Bitstream definition in FPGA:<\/strong> The file that configures the FPGA<\/a> (has a .bit extension). The bitstream gets loaded into an FPGA when ready for execution. Obtained after place and route, final result of the place and route phase.<\/p>\n

C\/C++:<\/strong> C++<\/a>\u00a0is a general-purpose object-oriented programming (OOP) language, developed by Bjarne Stroustrup, and is an extension of the\u00a0C\u00a0language. It is therefore possible to code\u00a0C++\u00a0in a “C\u00a0style” or “object-oriented style.<\/p>\n

Assembly (Language):<\/strong> An assembly language, often abbreviated asm, is any low-level programming language, in which there is a very strong correspondence between the assembly program statements and the architecture’s machine code instructions.<\/p>\n

Binary:<\/strong> Binary\u00a0<\/a>(or base-2) a numeric system that only uses two digits \u2014 0 and 1.\u00a0Computers\u00a0operate in\u00a0binary,meaning\u00a0they store data and perform calculations using only zeros and ones.<\/p>\n

Synthesis:<\/strong> Process of creating a netlist from a circuit description described using\u00a0HDLs<\/a>\u00a0(Hardware Description Language),\u00a0HLLs<\/a>\u00a0(High Level Language),\u00a0GUI<\/a>\u00a0(Graphical User Interfaces).<\/p>\n

Serial Terminal Application:<\/strong>\u00a0 An example of this is Tera Term, which is an open-source, free, software implemented, terminal emulator program. It emulates different types of computer terminals, from DEC VT100 to DEC VT382. It supports telnet, SSH 1 & 2 and serial port connections.<\/p>\n

FPGA chip definition:<\/strong> Unlike microcontrollers<\/a> where you only have control over the software, with FPGA you have control over the hardware as well. There is no processor to run software on, at least until you design one! You can configure an FPGA to be something as simple as an and gate, or something as complex as a multi-core processor. To create your design, you write some HDL (H<\/strong>ardware\u00a0D<\/strong>escription\u00a0L<\/strong>anguage). You then\u00a0synthesize<\/em>\u00a0your HDL into a bit file which you can use to configure the FPGA.\u00a0SoC (System on Chip) is used to distinguish between Zynq and non-Zynq parts (Zynq is an SoC which includes a processor).<\/span><\/p>\n

FPGA Board:\u00a0<\/strong>A PCB that the FPGA is designed to fit, typically offering multiple peripherals. Digilent examples include:\u00a0the Genesys ZU<\/a>, Basys 3<\/a>, \u00a0Nexys A7<\/a>, Cmod A7<\/a>, Arty S7<\/a>, Arty Z7<\/a>, Cora Z7<\/a>, Arty A7<\/a>, Nexys Video<\/a>, Eclypse Z7<\/a>, Zybo Z7<\/a>, and Cmod S7.<\/a> All can be found on our FPGA product page<\/a>.<\/p>\n

FPGA fabric:<\/strong> \u00a0The internal structure of an FPGA.<\/a> The various devices that the FPGA contains, the type of interconnect, the add-on features and so on. For example, a typical FPGA from Xilinx or Altera has a\u00a0combinatorial logic block<\/em>(CLB) which typically consists of a lookup table (LUT) which can be configured for 2 to 7 inputs, an adder and a D flip-flop. This forms the\u00a0logic element<\/em>\u00a0in the FPGA.\u00a0<\/em>The FPGA also contains other blocks like phase locked loops (PLL), I\/O buffers, block memory (BRAM), Digital Signal Processing (DSP) blocks and in some cases macro blocks which function as a PCIe controller, Gigabit Ethernet controller, Serializer\/Deserializer (SERDES) and off late even large blocks like video codecs (h.264 and h.265 in Zynq Ultrascale+). All of these blocks are programmable and configurable via RTL but need not be designed as we’d do in the ASIC flow. (Except for the FPGA manufacturer of course).<\/p>\n

LUT definition for FPGA:<\/strong>\u00a0 A LUT<\/a>, or l<\/strong>ooku<\/strong>p t<\/strong>able is a fast way to realize a complex function in\u00a0digital logic. The address is the function input, and the value at that address is the function output. The advantage is that computing the function only takes a single memory lookup regardless of the complexity of the function, so it is very fast.<\/p>\n

Serial Connection:<\/strong> A\u00a0serial<\/em>\u00a0port is a\u00a0serial communication<\/em>\u00a0interface through which information transfers in or out one bit at a time (in contrast to a parallel port).<\/p>\n

Peripherals:<\/strong> Fixed\u00a0peripherals\u00a0<\/a>that are conventionally found on microcontrollers and microprocessors normally surround the hard-core processors. These\u00a0peripherals\u00a0include interfaces like serial ports, parallel ports, and Ethernet ports.<\/p>\n

Peripherals can also refer to hardware added on a design. For example, attaching a PCAM to the FPGA for computer vision applications.<\/p>\n

Hard-core vs. soft-core:<\/strong> A\u00a0hard-core\u00a0processor is a processor that’s actually physically implemented as a structure in the silicon. Basically, you can add a\u00a0soft-core\u00a0processor to a FPGA-based system after it’s already designed. However, adding a\u00a0hard-core\u00a0processor requires either a different FPGA, or an additional chip on the board.<\/p>\n

FPGA firmware:<\/strong> Though the code deployed on the FPGA<\/a> is sometimes referred to as its firmware, this is a slight misconception. Firmware\u00a0is indeed embedded and dedicated code, but the code is executed.\u00a0FPGA code is written in a description language, then is interpreted, synthesized, and ultimately produces hardware. So, I see it fit to refer to the\u00a0FPGA, when it is configured, as hardware, and to the code itself as a description language.<\/p>\n

IP core:<\/strong> An\u00a0IP\u00a0(intellectual property)\u00a0core\u00a0is a block of logic or data that is used in making a field programmable gate array (\u00a0FPGA\u00a0) or application-specific integrated circuit ( ASIC ) for a product. They are reusable\/portable between many different designs.<\/span><\/p>\n

FPGA clock:<\/strong> All logic executing within the fabric of an FPGA must be based upon one or more timeframe references more commonly called \u201cclocks.<\/a>\u201d On the FPGA module, clocks are used to synchronize read\/write operations, synchronize data transmission and capture, control the timing of data processing, and prepare data for storage. For example, it may take some multiple of 8 clock cycles to process and prepare a single 8-bit byte of data for storage in a memory device.<\/p>\n

Synchronous<\/strong>: Typically describing a system that operates on a single clock.<\/span><\/p>\n

FPGA architecture:<\/strong> FPGA architecture\u00a0<\/a>is how the chip is designed\/structured, rather than the chip itself.<\/span>\u00a0The FPGA Architecture consists of three major components<\/p>\n