{"id":19765,"date":"2017-03-29T10:00:06","date_gmt":"2017-03-29T17:00:06","guid":{"rendered":"https:\/\/blog.digilentinc.com\/?p=19765"},"modified":"2026-09-26T07:31:33","modified_gmt":"2026-09-26T14:31:33","slug":"creating-and-programming-our-first-fpga-project-part-4","status":"publish","type":"post","link":"https:\/\/digilent.com\/blog\/creating-and-programming-our-first-fpga-project-part-4\/","title":{"rendered":"Creating and Programming our First FPGA Project"},"content":{"rendered":"

Welcome back to the Digilent blog!<\/span><\/p>\n

This guide walks through the entire process, start to finish: getting the required files, creating the Vivado project, writing the Verilog and XDC code, and generating and programming the bitstream.<\/span><\/p>\n

While it would be nice to think that we can simply write up an FPGA program and configure our board with it and move on to the next program,<\/span> FPGAs are complex enough<\/span><\/a> that it is a good idea to add in some pre-made board files to help smooth out the programming process. I will be using <\/span>Digilent’s Arty<\/span><\/a> throughout the duration of this tutorial and Verilog as my FPGA programming language of choice and the 2016.4 WebPACK edition of Xilinx’s Vivado Design Suite, though boards like the <\/span>Basys 3<\/span><\/a>, <\/span>Nexys A7<\/span><\/a>, <\/span>Cmod A7<\/span><\/a>, <\/span>Cmod S7<\/span><\/a>, and <\/span>Arty S7<\/span><\/a> will also work.<\/span><\/p>\n

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Digilent’s Arty<\/figcaption><\/figure>\n

The two files we will be looking for are the Arty XDC (Xilinx Design Constraints) file and the Arty board file. The XDC file is used by Vivado to associate the names of the inputs and outputs we “create” in our Verilog code to actual pins on the FPGA chip. The board file is used to group different sets of pins on the FPGA together so that they can be readily used when configuring various IP blocks; we won’t be using any IP blocks in this tutorial, but it’s nice to already have the board file installed for the future (and makes it much easier to tell Vivado which FPGA we are working with when we are initially creating a project).<\/span><\/p>\n

To get the Arty board file, go ahead and download the Digilent board files from the<\/span> Digilent GitHub account<\/span><\/a> (at the direct download link or<\/span> view the board files natively in GitHub here<\/span><\/a>). Within the board files .zip folder, you’ll want to extract the “Arty” folder (and everything inside it) to the board_files folder that is inside the Xilinx directory, which you already have installed. On a Windows system, the default location for this board_files folder is <\/span>C:\\Xilinx\\Vivado\\2016.4\\data\\boards\\board_files<\/span>; copy the whole “Arty” folder structure into this folder.<\/span><\/p>\n

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Download the Digilent board files from the Digilent GitHub<\/figcaption><\/figure>\n

Next, we’ll want to get the XDC file for the Arty so that we can inform Vivado what physical pins we wish to use with our project. A master XDC file for the Arty (and all of<\/span> Digilent’s FPGA boards<\/span><\/a>) can be found in their respective Resource Centers on our Wiki. The Arty Resource Center is<\/span> here<\/span><\/a>, with the Master XDC file available in the box on the right-hand side of the screen underneath “Design Resources”. Once you have downloaded the Master XDC file, save it somewhere on your computer where you can easily find it again since we’ll need to be able to tell Vivado where to find the file when we create our project.<\/span><\/p>\n

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Where you can find the Master XDC file on a Digilent FPGA Resource Center<\/figcaption><\/figure>\n

Let’s go ahead and create ourselves a new Vivado project. To do so, open up the Vivado application and click on the “Create New Project” button located in the upper left-hand corner, and then click “Next” on the next screen that appears to confirm that we do want to create a new project.<\/span><\/p>\n

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Choose a new project on the Vivado opening screen<\/figcaption><\/figure>\n
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Friendly instructions from Vivado on how to create a project.<\/figcaption><\/figure>\n

We’ll then be able to name our project and choose where we would like Vivado to save and generally store our project on our computer. The big caveat here is that both the name of our Vivado project, as well as the file path that our Vivado project is stored in, must not have any spaces in it. Otherwise, you will run into some issues when Vivado is trying to create a project. Once you have chosen your name and file location, click “Next”, and on the next page choose to create an RTL project (the first option), leaving the box to “Do not specify sources at this time” unchecked.<\/span><\/p>\n

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Name your Vivado project and choose where to save it<\/figcaption><\/figure>\n
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Create an RTL project in Vivado<\/figcaption><\/figure>\n

On the next page, choose “Create File” so we can create our own source file now rather than having to manually create it later. A “Create Source File” window will pop up where we can choose our file type of Verilog (for this tutorial) and the name of our Verilog source file. A typical name for these source files that will be the primary file that runs our program is “top.v” to signify that it is the file that runs (and calls) everything involved with that file. Once you’re done with that, click “OK” and then click “Next”.<\/span><\/p>\n

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Create a HDL source file<\/figcaption><\/figure>\n
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Name the HDL source file that you are creating<\/figcaption><\/figure>\n

Go ahead and click “Next” on the page asking about IP cores since we don’t have any to add for this tutorial. On the next page for Add Constraints, we will want to choose to “Add Files”; the file we are looking for is the Master XDC file that we added previously. Once you have found and chosen this file, be sure to check the “Copy constraints files into project” box so that the original file does not get altered when we change it later on in the tutorial.<\/span><\/p>\n

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Choose to add a constraints file<\/figcaption><\/figure>\n
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Choose the constraints file we’ve already saved<\/figcaption><\/figure>\n
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Be sure to make a copy of the constraints file in your project<\/figcaption><\/figure>\n

Now we’ll need to select the FPGA that we are using; there are two different ways that we can approach this. We can either manually search for the part (you can find the FPGA part on Digilent FPGA boards by looking at their respective Resource Centers underneath the “Documentation” section on the right-hand side of the page). Alternatively, if you click on the “Boards” button and you have added the board file for your respective board (like we did for the Arty board above), you will be able to easily find your board in the list that appears when you select <\/span>Digilent<\/span><\/a> as the vendor.<\/span><\/p>\n

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Choose your FPGA by part number<\/figcaption><\/figure>\n
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Choose your FPGA by board file.<\/figcaption><\/figure>\n

After clicking “Next” after choosing our FPGA board, we will be presented with a final confirmation screen of our new project that we’re about to create. If you’re happy with the summary, go ahead and choose “Finish”.<\/span><\/p>\n

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Confirm that your project has the initial settings that you want.<\/figcaption><\/figure>\n

Let’s go ahead and modify our new project. The first window we will encounter is a wizard that lets us configure a new module; this is a part of a Verilog project where we can define the inputs and outputs for our project that we are creating. For this tutorial, we are only assigning an LED to a value of a switch, so we only need to create a single input and a single output (leaving the “Bus” box unchecked for both of them). I named my input and output “sw” and “led”, respectively, although you can name whatever you would prefer. You can also rename your module (if you kept the top.v suggestion as the file name from before, your module will currently be called “top”) to something a little more intuitive if you so desire.<\/span><\/p>\n

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Our first look at Vivado and the location of our source file<\/figcaption><\/figure>\n

Finally, we’re at the main Vivado GUI where we can actually “do stuff”, i.e., add the code to our Verilog module that tells Vivado what the module is supposed to do, change the XDC file to inform Vivado what physical pins you intend to use with your module, add IP if you choose to do so, and more. Let’s go ahead and add in the Verilog code for our top module.<\/span><\/p>\n

What we intend to do for this particular tutorial is have the state of the LED be dependent upon the state of the associated switch. The keyword that will best model this behavior in Verilog is assign<\/code>. Double-click on the top module code in the Sources window in the Design Sources folder to have it open up in the editor in the upper right-hand side of the GUI. The line of code that we will want to add is<\/span><\/p>\n

assign led = sw;<\/code><\/p>\n

It will go between the closing curly brace and semicolon surrounding the named module that we just created in the wizard. That’ll be all we need to do in the Verilog Module for this project.<\/span><\/p>\n

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Top module wizard in Vivado<\/figcaption><\/figure>\n
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We have added in our code to our top module<\/figcaption><\/figure>\n

The XDC file will require a little more manipulation and is the focal point of what makes FPGAs so versatile to the end user; when this file is edited, we are, in essence, informing Vivado where all of our inputs and outputs on our “black box” are physically located on the FPGA. Vivado does all the heavy lifting in terms of how to actually connect point A to point B using the HDL we created in the Verilog module, while we just have to worry about some external aesthetics. Naturally, this analogy falls short once you get into more complex designs, but it’s fun to think that way. But back to the XDC file itself; how do we actually edit it?<\/span><\/p>\n

You can find the XDC file in the upper left corner in the Sources window in the Constraints folder. Double-clicking on it will bring up the XDC file in the upper right-hand side of the Vivado GUI. If you are using a master XDC file for a Digilent board, you will notice that everything in the XDC file is currently commented out with a # sign so that Vivado does not interpret it as code to be used. What we will want to do with this project (having the state of an LED be assigned to the state of a switch) is enable our LED and switch of choice.<\/span><\/p>\n

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Where to find the constraints file in Vivado<\/figcaption><\/figure>\n
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A brief look at the XDC file<\/figcaption><\/figure>\n

It’s important to note here that we can’t just use any pin for our LED and switch, despite how I described the XDC file in the previous paragraph. As I am looking to use one of the embedded switches and LEDs already present on the Arty (as that is my board of choice), those components are already pre-wired to a pin on the FPGA and can’t be re-routed without making physical modifications to the board. However, if I instead had an external switch and LED, in theory I could then attach those to any pin in the FPGA that I could physically access. While this might not seem all that different from a microcontroller, this really comes into play when you start to create hardware controllers, but you can place as many as you want wherever you need to rather than being limited to whatever that microcontroller has built into it.<\/span><\/p>\n

The Digilent master XDC files are organized by physical group on the FPGA, such as switches, Pmod Headers, Ethernet PHY, and the like. For this tutorial project, we can scroll down to the switches and LEDs section and uncomment a single line from both of them by removing the #<\/code> sign from the front of the associated line of code. Then, we need to edit the name of the pin (between the curly braces immediately following the get_ports<\/code> statement) to match whatever we called it in our Verilog module.<\/span><\/p>\n

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Our edited XDC file names match our module names<\/figcaption><\/figure>\n

Phew! The Verilog module and XDC file are edited and ready to go! After saving this project, we’ll then be able to generate our bitstream and program the FPGA.<\/span><\/p>\n

Let’s go ahead and generate the bitstream! In practice, you would be able to simply click on the “Generate Bitstream” button on the left-hand side of the GUI under the “Program and Debug” subsection, but we’ll manually walk through each of the required preceding steps. Presuming your Verilog module and XDC file are already edited to your taste and are saved, go ahead and click on “Run Synthesis” under the “Synthesis” subsection on the left-hand side of the GUI.<\/span><\/p>\n

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Click the run synthesis button to start the process of programming our board.<\/figcaption><\/figure>\n

The first time running synthesis (and later times as well if you don’t check the “Don’t show this dialog again” box), you’ll be presented with a wizard showing you some synthesis options. What we want to do is leave our “Launch directory” in the “Default Launch Directory” folder and to choose to have the launch run on the local host (your computer) rather than only generating the scripts. You’ll also be given a dropdown option to choose the “Number of jobs” that Vivado can use; this is essentially the number of computer cores that Vivado is allowed to use on your computer. I recommend choosing the maximum number that is available to you, as getting a bitstream ready to program an FPGA is very computer-intensive. As a side note, the whole combination of synthesis, implementation, and the generation of the bitstream can take quite a bit of time (more than 10 minutes in some cases) since Vivado processes a ton of things hidden to the user and works with the entire FPGA and not just what we are physically utilizing. Click OK after you’re happy with your selections and wait for the synthesis process to complete, which may take a couple of minutes depending on your computer.<\/span><\/p>\n

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You’ll see a number of options to run the synthesis procedure.<\/figcaption><\/figure>\n

Once it’s done, you’ll then be presented with a pop-up asking you what you would like to do next. Go ahead and choose the “Run Implementation” option. You’ll then see a similar wizard for the implementation process, where you’ll want to keep the default options, but have the maximum number of cores (jobs) be used. This process also can take a couple of minutes.<\/span><\/p>\n

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Run the implementation after the synthesis is completed.<\/figcaption><\/figure>\n

You’ll receive a second popup asking what you want to do next. You’ll want to choose “Generate Bitstream”, but as a side note, you may not necessarily want to click on the “don’t show this dialog again” box this time because if you are designing a circuit for your FPGA to run, you may just want to check to see if Vivado was able to successfully make it through synthesis and implementation. If there is an error, you would not want to generate a faulty bitstream. You’ll then be able to choose some bitstream generation options, much like for synthesis and implementation. When you are happy with your selections, click OK to have Vivado generate the bitstream.<\/span><\/p>\n

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Choose to generate the bitstream after implementation is finished.<\/figcaption><\/figure>\n

After another few minutes, the bitstream will finally be generated, and all we have left to do is program our FPGA with it! You’ll see another helpful popup where we will get the option to choose to open the Hardware Manager, which is where we will be able to make sure Vivado is connected to our FPGA.<\/span><\/p>\n

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Open the Hardware Manager after the bitstream is generated.<\/figcaption><\/figure>\n

If your FPGA is not connected to your computer already (or if it’s connecting for the first time) you’ll see a green bar at the top that indicates that no hardware target (FPGA) is currently open. After you connect your FPGA to your computer, typically via a micro USB cable, and confirm that the LED power indicator lights turn on, go ahead and click on the “Open Target” button in the green bar and then choose “Auto Connect”.<\/span><\/p>\n

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Choose auto-connect after opening your hardware manager in Vivado.<\/figcaption><\/figure>\n

We’ll then be asked to choose the bitstream file to load the FPGA with (we don’t have to worry about the debug probes since we don’t have any in this project). The bitstream file is a little non-intuitive to find; You can find it in your project directory under <\/span>yourProjectName.runs<\/span>, then <\/span>impl_1<\/span>. Select the <\/span>.bit<\/span> file inside that folder, and then choose the .bit file that you see. In this tutorial, the Verilog module is named top, so the bitstream is called top.bit. Click OK to confirm your selection of the bitstream and then click “Program” (you can leave the “Enable end of startup check” either enabled or disabled). Luckily, the programming process itself will take under 10 seconds, so that’s a nice change of pace. (Arty Programming Guide keeps going, into the reference for Arty programming<\/a>.<\/span>)<\/span><\/p>\n

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We need to choose our bitstream file in Vivado.<\/figcaption><\/figure>\n
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Where to find the bitstream in Vivado.<\/figcaption><\/figure>\n

And we’re finally done! The way I set up this tutorial (and my XDC file), I have the first switch (SW0 on the silkscreen) on the Arty controlling the state of the first monocolored LED (LD4), as evidenced in the picture below.<\/span><\/p>\n

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The Arty board in action.<\/figcaption><\/figure>\n

I hope you all enjoyed this tutorial!<\/span><\/p>\n

Please feel free to comment with any questions you have or any other tutorials you would like to see in the future! Additionally, check out <\/span>our Wiki<\/span><\/a> for more resources on this project.<\/span><\/p>\n

0<\/span><\/a><\/div><\/div>
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<\/div>","protected":false},"excerpt":{"rendered":"

Get ready for part four of the Creating and Programming our FPGA series: Generating the Bitstream and Programming the FPGA!<\/p>\n","protected":false},"author":17,"featured_media":19321,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_jetpack_newsletter_access":"","_jetpack_dont_email_post_to_subs":false,"_jetpack_newsletter_tier_id":0,"_jetpack_memberships_contains_paywalled_content":false,"_jetpack_feature_clip_id":0,"_jetpack_memberships_contains_paid_content":false,"footnotes":"","jetpack_post_was_ever_published":false},"categories":[4327,35],"tags":[144,453],"ppma_author":[4469],"class_list":["post-19765","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-projects","category-fpga","tag-tutorial-2","tag-vivado"],"jetpack_featured_media_url":"https:\/\/digilent.com\/blog\/wp-content\/uploads\/2017\/02\/FPGAs-have-a-lot-going-on-with-them.png","jetpack_sharing_enabled":true,"authors":[{"term_id":4469,"user_id":17,"is_guest":0,"slug":"jamescolvin","display_name":"James Colvin","avatar_url":"https:\/\/secure.gravatar.com\/avatar\/8aa85f7d11711acc7e571e1ed26c901b614a7064a2e15e522f54d9f26792ea9e?s=96&d=mm&r=g","author_category":"","user_url":"","last_name":"Colvin","last_name_2":"","first_name":"James","first_name_2":"","job_title":"Applications Engineer \/ Technical Support Engineer \/ Product Support Engineer \/ Technical Writer \/ the person to bother about T&M and JTAG when the senior design engineer is busy","description":"A local Digilent employee who is sometimes tricked into making other content besides documentation and supporting customers on the Digilent Forum, but then I get to write a little more informally so that's a plus. \r\n\r\nA sassy engineer, lover of puns and dad jokes, father and husband. \r\n\r\nI know both way too much and simultaneously almost nothing about a number of nerdy topics. If you want to hear me rant, ask me what data rate USB C operates at."}],"post_mailing_queue_ids":[],"_links":{"self":[{"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/posts\/19765","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/users\/17"}],"replies":[{"embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/comments?post=19765"}],"version-history":[{"count":6,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/posts\/19765\/revisions"}],"predecessor-version":[{"id":32632,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/posts\/19765\/revisions\/32632"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/media\/19321"}],"wp:attachment":[{"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/media?parent=19765"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/categories?post=19765"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/tags?post=19765"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/digilent.com\/blog\/wp-json\/wp\/v2\/ppma_author?post=19765"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}